Abstract: Each unit circuit includes a thin film transistor (first stabilization transistor) having a gate terminal to which a clear signal which goes to an on level when a frame period ends applied, a drain terminal connected to a charge holding node, and a source terminal to which a potential of an off level is applied. Here, a gate length of the thin film transistor is set to be larger than gate lengths of other charge holding node turn-off transistors. Alternatively, a multi-gate structure is adopted for the thin film transistor and a single gate structure is adopted for the other charge holding node turn-off transistors.

Abstract: Each unit circuit that constitutes each of stages of a shift register is provided with a charge supply unit including a third node whose potential becomes high level at identical timing with a first node (a node for holding an electric charge in order to output a scanning signal (output signal) at high level), and capable of supplying an electric charge to the first node throughout a period after the potential of the third node becomes high level until the scanning signal (output signal) at high level is outputted. Here, all of the unit circuits within the shift register have an identical configuration.

Abstract: An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.

Abstract: A unit circuit 4 that forms each stage of a shift register is configured by a transfer unit 401 having substantially the same configuration as that of the conventional unit circuit, a state memory unit 402 configured to store a state of a first node N1 within the transfer unit 401 when suspension of scanning is performed, and a connecting unit 403 that connects the state memory unit 402 with the transfer unit 401 so that an electric charge based on an output signal QX from the state memory unit 402 is supplied to the first node N1. A clock operation of control clock signals CKX and CKXB for controlling an operation of the state memory unit 402 is performed when a clock operation of a gate clock signal is suspended.

Abstract: An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.

Abstract: A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second int

Abstract: A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second int

Abstract: Disclosed is a signal distribution device which is provided with: supply lines (5) for supplying input signals to switching elements in signal distribution circuits; and distribution lines (6) for distributing the input signals to output terminals via the switching elements. The corresponding one of the supply lines (5) and at least one of the distribution lines (6) each have an extension section (5a) and an extension section (5b) which extend in an extending direction of a control line (13). A selection signal for switching on/off the associated switching element is applied to the control line (13). The extension sections (5a and 5b) are formed at positions that do not overlap the edge portions of the control line (13) in the extending direction thereof.

Abstract: A driving circuit includes digital/current converting (DCC) circuits one for each data line. The DCC circuit charges a capacitor with a reference current according to a supplied signal from a shift register. The DCC circuit stores a current value of the reference current and outputs the current value to a data line via a switching element turned on by a digital image data signal of a single line supplied from a line latch. The output value of each DCC circuit is reset one after another in every select scan period in which an OFF signal is sent to all the data lines. Thus, the reset of the output value and the output of the image data signal can be successively carried out within one frame period, so the data applied to the pixel circuit with the DCC circuits one for each data line.

Abstract: Disclosed is a signal distribution device which is provided with: supply lines (5) for supplying input signals to switching elements in signal distribution circuits; and distribution lines (6) for distributing the input signals to output terminals via the switching elements. The corresponding one of the supply lines (5) and at least one of the distribution lines (6) each have an extension section (5a) and an extension section (5b) which extend in an extending direction of a control line (13). A selection signal for switching on/off the associated switching element is applied to the control line (13). The extension sections (5a and 5b) are formed at positions that do not overlap the edge portions of the control line (13) in the extending direction thereof.

Abstract: A driving circuit of a display device includes digital/current converting (DCC) circuits, one for each data line. The DCC circuit operates to charge a capacitor with a reference current according to a supplied signal from a shift register. The DCC circuit stores a current value of the reference current and outputs it to a data line via a switching element that has been turned on by a digital image data signal of a single line supplied from a line latch. The output value of each DCC circuit is reset, one after another, in every select scan period in which an OFF signal is sent to all the data lines. In this way, the reset of the output value and the output of the image data signal can be successively carried out within one frame period, enabling the data to be applied to the pixel circuit.

Abstract: A pixel circuit (Aij) has a capacitor (Cs) having one of ends connected with a gate terminal of a DTFT (driving TFT) and the other end connected with a capacitance feedback line (CSi), a current-voltage conversion circuit (14) having an input terminal to which a feedback current flowing to a DDTFT (dummy driving circuit) is input when a predetermined potential is supplied to a gate terminal of the DDTFT having TFT characteristics substantially same as those of the DTFT in the pixel circuit (Aij) during a selected period for converting the feedback current into voltage and outputting a potential according to the voltage from an output terminal, and a changeover switch (CSW) for connecting the capacitance feedback line (CSi) corresponding to the pixel circuit (Aij) with the current-voltage conversion circuit (14) during the selected period and connecting the capacitance feedback line (CSi) corresponding to the pixel circuit (Aij) during a non-selected period with a constant potential supply line for supplying a

Abstract: A driving circuit of display device includes digital/current converting (DCC) circuits one for each data line. The DCC circuit operates to charge a capacitor with a reference current according to a supplied signal from a shift register. The DCC circuit stores a current value of the reference current and outputs it to a data line via a switching element that has been turned on by a digital image data signal (H) of a single line supplied from a line latch. The output value of each DCC circuit is reset one after another in every select scan period in which an OFF signal is sent to all the data lines. In this way, the reset of the output value and the output of the image data signal can be successively carried out within one frame period, enabling the data to be applied to the pixel circuit with the DCC circuits provided one for each data line. This simplifies the driving circuit that drives the pixel circuits provided with an electro-optic element and disposed in a matrix.

Abstract: An organic electroluminescent panel has excellent reliability of luminance of emitted light, and an organic electroluminescent display device includes such an organic electroluminescent panel. The organic electroluminescent panel includes a structure in which the first electrode, an organic layer including at least a light-emitting layer, the second electrode are stacked in this order on a substrate having a surface on which an organic insulating film is formed, wherein the organic electroluminescent panel further includes an inorganic insulating film, the inorganic insulating film covers the organic insulating film and the first electrode, the inorganic insulating film has an opening in a display region and an opening in a non-display region, and the opening in the display region is formed on the first electrode.

Abstract: A pixel circuit (Aij) has a capacitor (Cs) having one of ends connected with a gate terminal of a DTFT (driving TFT) and the other end connected with a capacitance feedback line (CSi), a current-voltage conversion circuit (14) having an input terminal to which a feedback current flowing to a DDTFT (dummy driving circuit) is input when a predetermined potential is supplied to a gate terminal of the DDTFT having TFT characteristics substantially same as those of the DTFT in the pixel circuit (Aij) during a selected period for converting the feedback current into voltage and outputting a potential according to the voltage from an output terminal, and a changeover switch (CSW) for connecting the capacitance feedback line (CSi) corresponding to the pixel circuit (Aij) with the current-voltage conversion circuit (14) during the selected period and connecting the capacitance feedback line (CSi) corresponding to the pixel circuit (Aij) during a non-selected period with a constant potential supply line for supplying a

Abstract: The present invention provides a light-emitting circuit board and a light-emitting display device, which can reduce a frame region (a space between a side of the board and a pixel region) on a board. The light-emitting circuit board of the present invention is a light-emitting circuit board comprising: on a board, a plurality of pixels each including a first electrode, a light-emitting layer, and a second electrode, stacked in this order; a driver circuit; and an external terminal, wherein the driver circuit is connected to the external terminal; the second electrode of the pixel and the external terminal are connected to each other by a wiring through an off-pixel contact; and the wiring is disposed to overlap with at least part of the driver circuit.

Abstract: An organic electroluminescent panel has excellent reliability of luminance of emitted light, and an organic electroluminescent display device includes such an organic electroluminescent panel. The organic electroluminescent panel includes a structure in which the first electrode, an organic layer including at least a light-emitting layer, the second electrode are stacked in this order on a substrate having a surface on which an organic insulating film is formed, wherein the organic electroluminescent panel further includes an inorganic insulating film, the inorganic insulating film covers the organic insulating film and the first electrode, the inorganic insulating film has an opening in a display region and an opening in a non-display region, and the opening in the display region is formed on the first electrode.

Abstract: A driving circuit of display device includes digital/current converting (DCC) circuits one for each data line. The DCC circuit operates to charge a capacitor with a reference current according to a supplied signal from a shift register. The DCC circuit stores a current value of the reference current and outputs it to a data line via a switching element that has been turned on by a digital image data signal (H) of a single line supplied from a line latch. The output value of each DCC circuit is reset one after another in every select scan period in which an OFF signal is sent to all the data lines. In this way, the reset of the output value and the output of the image data signal can be successively carried out within one frame period, enabling the data to be applied to the pixel circuit with the DCC circuits provided one for each data line. This simplifies the driving circuit that drives the pixel circuits provided with an electro-optic element and disposed in a matrix.

Abstract: A driving circuit of display device includes digital/current converting (DCC) circuits one for each data line. The DCC circuit operates to charge a capacitor with a reference current according to a supplied signal from a shift register. The DCC circuit stores a current value of the reference current and outputs it to a data line via a switching element that has been turned on by a digital image data signal (H) of a single line supplied from a line latch. The output value of each DCC circuit is reset one after another in every select scan period in which an OFF signal is sent to all the data lines. In this way, the reset of the output value and the output of the image data signal can be successively carried out within one frame period, enabling the data to be applied to the pixel circuit with the DCC circuits provided one for each data line. This simplifies the driving circuit that drives the pixel circuits provided with an electro-optic element and disposed in a matrix.

Abstract: A driving circuit of display device includes digital/current converting (DCC) circuits one for each data line. The DCC circuit operates to charge a capacitor with a reference current according to a supplied signal from a shift register. The DCC circuit stores a current value of the reference current and outputs it to a data line via a switching element that has been turned on by a digital image data signal (H) of a single line supplied from a line latch. The output value of each DCC circuit is reset one after another in every select scan period in which an OFF signal is sent to all the data lines. In this way, the reset of the output value and the output of the image data signal can be successively carried out within one frame period, enabling the data to be applied to the pixel circuit with the DCC circuits provided one for each data line. This simplifies the driving circuit that drives the pixel circuits provided with an electro-optic element and disposed in a matrix.