Patents by Inventor Akira Takamatsu
Akira Takamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10006143Abstract: Providing a power-supplying member capable of desirably performing plating for a long period of time. A second power-supplying member is brought into contact with an article to be plated to apply negative voltage to the article. The article is disposed in a state such that a space in which a plating solution flows is defined between an anode and the article. The second power-supplying member includes a center member made from copper and a covering member made from titanium and covering at least a part of a periphery of the center member. The part is wetted with the plating solution.Type: GrantFiled: June 6, 2014Date of Patent: June 26, 2018Assignee: KYB CORPORATIONInventors: Yoshitaka Mochizuki, Toshihisa Miyazaki, Akira Takamatsu
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Patent number: 10007763Abstract: A drug prescribing system that can prevent a wrong drug from being taken during picking is provided. A drug prescribing system includes a host computer including an input device through which prescription data based on a prescription is input, a drug dispensing apparatus in which drugs are housed in advance, and that dispenses a drug in accordance with the prescription data, and a picking inspection apparatus that conducts a picking inspection for a drug picked in accordance with the prescription data. The drug dispensing apparatus outputs supplementary information on a drug that is not dispensed with the drug dispensing apparatus and needs to be supplemented. The picking inspection apparatus receives an input of the supplementary information, and conducts the picking inspection for a supplementary drug supplemented based on the supplementary information.Type: GrantFiled: April 19, 2013Date of Patent: June 26, 2018Assignee: TAKAZONO TECHNOLOGY INCORPORATEDInventor: Akira Takamatsu
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Patent number: 10006137Abstract: Providing a holding device which can hold a plurality of types of workpieces and can reliably prevent a liquid in a liquid tank from leaking. The holding device includes a holding member configured to hold an article (workpiece) to be plated in a holding chamber. The article is disposed over a liquid tank in which a plating solution (liquid) flows and the holding chamber communicating with the liquid tank. The holding member has a plurality of abutting parts which closely abut against portions of an outer periphery of the article at a same level thereby to hold the article therebetween. The abutting parts are formed of a sponge sheet (elastic body) with chemical resistance. The holding device includes a pressurizing unit configured to supply air into the holding chamber to pressurize an atmosphere in the holding chamber while the article is held by the holding member.Type: GrantFiled: June 6, 2014Date of Patent: June 26, 2018Assignee: KYB CORPORATIONInventors: Yoshitaka Mochizuki, Toshihisa Miyazaki, Akira Takamatsu
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Publication number: 20160130714Abstract: Providing a holding device which can hold a plurality of types of workpieces and can reliably prevent a liquid in a liquid tank from leaking. The holding device includes a holding member configured to hold an article (workpiece) to be plated in a holding chamber The article is disposed over a liquid tank in which a plating solution (liquid) flows and the holding chamber communicating with the liquid tank. The holding member has a plurality of abutting parts which closely abut against portions of an outer periphery of the article at a same level thereby to hold the article therebetween. The abutting parts are formed of a sponge sheet (elastic body) with chemical resistance. The holding device includes a pressurizing unit configured to supply air into the holding chamber to pressurize an atmosphere in the holding chamber while the article is held by the holding member.Type: ApplicationFiled: June 6, 2014Publication date: May 12, 2016Applicant: KYB CORPORATIONInventors: Yoshitaka MOCHIZUKI, Toshihisa MIYAZAKI, Akira TAKAMATSU
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Publication number: 20160108542Abstract: Providing an anode capable of desirably performing plating for a long period of time. An anode is cylindrical and forms a space between an article to be plated and itself. A plating solution flows in the space. Positive voltage is applied to the anode. The anode includes an outer cylinder and an inner cylinder welded to be in contact with an inner surface of the outer cylinder. The inner cylinder is formed of a plate material made from platinum.Type: ApplicationFiled: June 6, 2014Publication date: April 21, 2016Applicant: KYB CORPORATIONInventors: Yoshitaka MOCHIZUKI, Toshihisa MIYAZAKI, Akira TAKAMATSU
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Publication number: 20160108540Abstract: Providing a power-supplying member capable of desirably performing plating for a long period of time. A second power-supplying member is brought into contact with an article to be plated to apply negative voltage to the article. The article is disposed in a state such that a space in which a plating solution flows is defined between an anode and the article. The second power-supplying member includes a center member made from copper and a covering member made from titanium and covering at least a part of a periphery of the center member. The part is wetted with the plating solution.Type: ApplicationFiled: June 6, 2014Publication date: April 21, 2016Applicant: KYB CORPORATIONInventors: Yoshitaka MOCHIZUKI, Toshihisa MIYAZAKI, Akira TAKAMATSU
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Publication number: 20150073819Abstract: A drug prescribing system that can prevent a wrong drug from being taken during picking is provided. A drug prescribing system includes a host computer including an input device through which prescription data based on a prescription is input, a drug dispensing apparatus in which drugs are housed in advance, and that dispenses a drug in accordance with the prescription data, and a picking inspection apparatus that conducts a picking inspection for a drug picked in accordance with the prescription data. The drug dispensing apparatus outputs supplementary information on a drug that is not dispensed with the drug dispensing apparatus and needs to be supplemented. The picking inspection apparatus receives an input of the supplementary information, and conducts the picking inspection for a supplementary drug supplemented based on the supplementary information.Type: ApplicationFiled: April 19, 2013Publication date: March 12, 2015Applicant: TAKAZONO TECHNOLOGY INCORPORATEDInventor: Akira Takamatsu
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Publication number: 20140190122Abstract: An object of the present invention is to provide a drug preparing system and a drug preparing device both capable of simplifying management of prescription data. A drug preparing system includes: a host computer that creates one piece of prescription data regarding a plurality of patients belong to a same group; a computer that obtains the prescription data created by the host computer and that creates drug preparation data based on the prescription data; and a packaging machine that prepares a drug based on the drug preparation data created by the computer.Type: ApplicationFiled: August 21, 2012Publication date: July 10, 2014Applicant: TAKAZONO TECHNOLOGY INCORPORATEDInventors: Kazuo Iimori, Akira Takamatsu
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Publication number: 20140174026Abstract: A packaging device eliminating waste of package paper can be provided. The packaging device includes: a computer that creates one packaging data based on prescription data regarding a plurality of patients belonging to the same group; and a packaging machine that packages a drug based on the packaging data created by the computer.Type: ApplicationFiled: August 21, 2012Publication date: June 26, 2014Applicant: TAKAZONO TECHNOLOGY INCORPORATEDInventors: Kazuo Iimori, Akira Takamatsu
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Patent number: 7402473Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: April 19, 2005Date of Patent: July 22, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Patent number: 7397104Abstract: A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.Type: GrantFiled: February 17, 2004Date of Patent: July 8, 2008Assignee: Elpida Memory, Inc.Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
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Publication number: 20070114631Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.Type: ApplicationFiled: January 16, 2007Publication date: May 24, 2007Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
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Patent number: 7208391Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.Type: GrantFiled: June 10, 2005Date of Patent: April 24, 2007Assignee: Renesas Technology Corp.Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
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Patent number: 7074691Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.Type: GrantFiled: June 10, 2005Date of Patent: July 11, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems C O., Ltd.Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
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Patent number: 7060589Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.Type: GrantFiled: February 11, 2005Date of Patent: June 13, 2006Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
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Publication number: 20050239257Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.Type: ApplicationFiled: June 10, 2005Publication date: October 27, 2005Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
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Publication number: 20050237603Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.Type: ApplicationFiled: June 10, 2005Publication date: October 27, 2005Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
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Publication number: 20050196935Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: ApplicationFiled: April 19, 2005Publication date: September 8, 2005Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20050148155Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.Type: ApplicationFiled: February 11, 2005Publication date: July 7, 2005Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
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Patent number: 6881646Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: March 21, 2003Date of Patent: April 19, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe