Patents by Inventor Akira Takamatsu

Akira Takamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040159883
    Abstract: A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 19, 2004
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Publication number: 20040106292
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: November 26, 2003
    Publication date: June 3, 2004
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Patent number: 6720234
    Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: April 13, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Patent number: 6717202
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: April 6, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iljima, Yuzuru Ohji
  • Patent number: 6693008
    Abstract: In order to fill in an isolation trench formed on a semiconductor substrate, the isolation trench is filled up to a predetermined middle position with a coating film first, and then an insulating film formed by a CVD method is deposited thereon. Additionally, the insulating film is polished by a CMP method, for example, so as to be ground. Thus, the isolation trench is filled with stacked films of the coating film and the insulating film. Further, an electrode pattern and a dummy pattern are formed on the semiconductor substrate, and the trench formed between these patterns is filled up to a predetermined middle position in its depth direction with the coating film. Then, a remaining depth portion of the trench is filled with the insulating film formed by a CVD method.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: February 17, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Publication number: 20030181020
    Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Application
    Filed: March 21, 2003
    Publication date: September 25, 2003
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Publication number: 20030148587
    Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
    Type: Application
    Filed: February 14, 2003
    Publication date: August 7, 2003
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Publication number: 20030139027
    Abstract: A gate electrode 8A of a memory cell selection MISFET Qs, which forms part of a memory cell, and gate electrodes 8B and 8C of an n-channel type MISFET Qn and a p-channel type MISFET Qp, which forms part of a logic LSI, are formed by an SiGe layer 28 and a W layer 29 deposited above the layer 28. A silicon nitride film 9 is formed above the gate electrodes 8A, 8B, and 8C to realize self-aligned contact holes (SAC).
    Type: Application
    Filed: January 17, 2003
    Publication date: July 24, 2003
    Inventors: Shuji Ikeda, Masayuki Kojima, Akira Takamatsu, Yasuko Yoshida
  • Publication number: 20030119276
    Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Application
    Filed: May 6, 2002
    Publication date: June 26, 2003
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Patent number: 6562695
    Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: May 13, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Suzuki, Hiroyuki Ichizoe, Masayuki Kojima, Keiji Okamoto, Shinichi Horibe, Kozo Watanabe, Yasuko Yoshida, Shuji Ikeda, Akira Takamatsu, Norio Ishitsuka, Atsushi Ogishima, Maki Shimoda
  • Patent number: 6559027
    Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: May 6, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Publication number: 20030038325
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Application
    Filed: October 17, 2002
    Publication date: February 27, 2003
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iijima, Yuzuru Ohji
  • Patent number: 6524927
    Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: February 25, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iljima, Yuzuru Ohji
  • Publication number: 20010026996
    Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Application
    Filed: May 1, 2001
    Publication date: October 4, 2001
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Patent number: 6242323
    Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
    Type: Grant
    Filed: August 16, 1999
    Date of Patent: June 5, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Patent number: 6057241
    Abstract: A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp<Tr.ltoreq.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: May 2, 2000
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yasushi Matsuda, Hideo Miura, Hirohiko Yamamoto, Masamichi Kobayashi, Shuji Ikeda, Akira Takamatsu, Norio Suzuki, Hirofumi Shimizu, Yasuko Yoshida, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
  • Patent number: 5951885
    Abstract: In a roller seam welding machine, the upper welding roller is led through a welding-force adjustment device with two spring elements. One spring is already effective when the initial deflection of the welding roller occurs. The other spring comes into operation only when a certain deflection (D) is reached. A marked improvement in weld quality can be obtained in this way, particularly at the start of the weld seam.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: September 14, 1999
    Assignee: Elpatronic AG
    Inventors: Nobuo Takahashi, Kiyoshi Kobayashi, Akira Takamatsu, Daniel Wenk
  • Patent number: 4869201
    Abstract: Can barrels of uniform diameter produced from a can barrel forming device by forming a square-shaped blank into a tubular shape with opposite edges joined linearly, are conveyed successively coaxially in spaced relation at a first speed with the joined areas of the can barrels directed upwardly. Then the can barrels are conveyed at a second speed slower than the first speed such that the open edges of the can barrels are coaxially spaced closely with small gaps left therebetween. Paint is continuously applied to the inner and outer surfaces of the joined areas while the can barrels are being conveyed at the second speed with the open edges of the can barrels being closely spaced by the small gaps.
    Type: Grant
    Filed: June 4, 1987
    Date of Patent: September 26, 1989
    Assignee: Hokkai Can Co., Ltd.
    Inventors: Nobuo Takahashi, Yuri Takeda, Akira Takamatsu, Yasushi Ito, Keizo Yamaguchi
  • Patent number: 4430225
    Abstract: A pressurized aeration tank is provided which comprises an inner barrel arranged on the tank axis and an axial-flow impeller of optimum characteristics mounted therein, the inner barrel and the outer barrel or body portion of the tank being particularly proportioned and arranged relative to each other to define in the tank a circuitous flow passage of minimal total resistance loss. With this tank structure, a highly improved plant efficiency of BOD removal is readily obtainable with the use of concentrated activated sludge and aerobic microorganisms, mainly of the Opercularia group, in a specified range of tank pressure.
    Type: Grant
    Filed: January 7, 1982
    Date of Patent: February 7, 1984
    Assignee: Kabushiki Kaisha Mitsui Miike Seisakusho, Tochigi Factory
    Inventors: Akira Takamatsu, Hiroshi Higuchi
  • Patent number: 4201843
    Abstract: New tylosin derivatives having at least one acyl group at the 3- and 4"-positions of tylosin, and the acid addition salts thereof, which inhibit the growth of various microorganisms including drug-resistant bacterial isolants and which produce high blood levels through oral administration are produced by a biochemical reaction using the microorganisms of the genus Streptomyces which are selected for their newly-found ability to acylate at least one of the 3- and 4"-positions of macrolide antibiotics; they are recovered from the reacted mixture by conventional methods for recovering macrolide antibiotics.
    Type: Grant
    Filed: February 27, 1978
    Date of Patent: May 6, 1980
    Assignee: Sanraku Ocean Co., Ltd.
    Inventors: Rokuro Okamoto, Tsumoru Fukumoto, Akira Takamatsu, Tomio Takeuchi