Patents by Inventor Akira Tanimoto
Akira Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180075630Abstract: A storage unit 81 stores information associating each of a plurality of prediction targets with a predictor-related index related to a predictor for predicting the prediction target. Scatter graph generation means 82 generates, based on the information stored in the storage unit 81, a scatter graph in which a symbol representing the prediction target of the predictor is located at a position determined by the predictor-related index in a coordinate space where the predictor-related index is defined as at least one dimension.Type: ApplicationFiled: March 23, 2015Publication date: March 15, 2018Applicant: NEC CorporationInventors: Akira TANIMOTO, Yousuke MOTOHASHI, Hiroki NAKATANI, Hiroshi KITAJIMA
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Patent number: 9911502Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.Type: GrantFiled: June 14, 2017Date of Patent: March 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
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Publication number: 20180052441Abstract: Reception means 81 receives an estimator learned using measured data up to a point of time in the past, verification data that is measured data from the point of time onward, and an update rule prescribing whether or not the estimator needs to be updated based on an evaluation index. Simulation means 82 simulates at least one of the evaluation index of the estimator and an update result of the estimator in a predetermined period, based on the update rule and an estimation result calculated by applying the verification data of the predetermined period to the estimator in chronological order.Type: ApplicationFiled: March 23, 2015Publication date: February 22, 2018Applicants: NEC CORPORATION, NEC Solution Innovators, Ltd.Inventors: Akira TANIMOTO, Yousuke MOTOHASHI, Mamoru IGUCHI
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Publication number: 20180039901Abstract: A predictor management system includes a storage unit 81 and update history management means 82. The storage unit 81 stores, in association with each of a plurality of prediction targets, an update history of a predictor corresponding to the prediction target. The update history management means 82 stores, in response to updating of a predictor, a prediction target of the predictor and an update time of the predictor in the storage unit 81 in association with each other.Type: ApplicationFiled: March 23, 2015Publication date: February 8, 2018Applicant: NEC CORPORATIONInventors: Akira TANIMOTO, Yousuke MOTOHASHI, Hiroki NAKATANI
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Publication number: 20170278576Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.Type: ApplicationFiled: June 14, 2017Publication date: September 28, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Koichi NAGAI, Katsuya MURAKAMI, Shinji HONJO, Satoru FUKUCHI, Akira TANIMOTO, lsao OZAWA
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Patent number: 9704593Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.Type: GrantFiled: March 9, 2015Date of Patent: July 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Nagai, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
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Publication number: 20170010639Abstract: A semiconductor device package includes a substrate including, on an edge thereof, a connector that is connectable to a host, a nonvolatile semiconductor memory device disposed on a surface of the substrate, a memory controller disposed on the surface of the substrate, an oscillator disposed on the surface of the substrate and electrically connected to the memory controller, and a seal member sealing the nonvolatile semiconductor memory device, the memory controller, and the oscillator on the surface of the substrate.Type: ApplicationFiled: March 1, 2016Publication date: January 12, 2017Inventors: Manabu MATSUMOTO, Katsuya MURAKAMI, Akira TANIMOTO, Isao OZAWA, Yuji KARAKANE, Tadashi SHIMAZAKI
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Patent number: 9543271Abstract: A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.Type: GrantFiled: August 27, 2015Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Manabu Matsumoto, Akira Tanimoto, Isao Ozawa
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Publication number: 20160268229Abstract: A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.Type: ApplicationFiled: August 27, 2015Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Manabu MATSUMOTO, Akira TANIMOTO, Isao OZAWA
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Publication number: 20160125950Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.Type: ApplicationFiled: March 9, 2015Publication date: May 5, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Koichi NAGAI, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
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Patent number: 9275947Abstract: A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.Type: GrantFiled: February 26, 2014Date of Patent: March 1, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami, Akira Tanimoto
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Publication number: 20150200008Abstract: According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate. The temperature sensor is provided at a position along an edge of the first surface, which is at a center portion separated away from corner portions. The plurality of solder balls is provided on a second surface that is at an opposite side of the first surface.Type: ApplicationFiled: July 1, 2014Publication date: July 16, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Isao OZAWA, Akira TANIMOTO, Eigo MATSUURA, Katsuya MURAKAMI, Yasuo KUDO, Koichi NAGAI
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Publication number: 20150137363Abstract: A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.Type: ApplicationFiled: February 26, 2014Publication date: May 21, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Isao OZAWA, Isao MAEDA, Yasuo KUDO, Koichi NAGAI, Katsuya MURAKAMI, Akira TANIMOTO
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Patent number: 8896111Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.Type: GrantFiled: March 12, 2013Date of Patent: November 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Tanimoto, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuke Dohmae
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Publication number: 20140070428Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.Type: ApplicationFiled: March 12, 2013Publication date: March 13, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Akira TANIMOTO, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuek Dohmae
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Publication number: 20130062758Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.Type: ApplicationFiled: March 16, 2012Publication date: March 14, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Takashi IMOTO, Yoriyasu Ando, Akira Tanimoto, Masaji Iwamoto, Yasuo Takemoto, Hideo Taguchi, Naoto Takebe, Koichi Miyashita, Jun Tanaka, Katsuhiro Ishida, Shogo Watanabe, Yuichi Sano
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Publication number: 20120248628Abstract: According to one embodiment, a semiconductor device includes a control element provided above a main surface of a substrate through a first adhesion layer, a second adhesion layer provided to cover the control element a first semiconductor chip provided on the second adhesion layer, a bottom surface area of the first semiconductor chip being larger than a top surface area of the control element, and at least one side of an outer edge of the control element projecting to an outside of an outer edge of the first semiconductor chip.Type: ApplicationFiled: September 15, 2011Publication date: October 4, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jun TANAKA, Koichi Miyashita, Yoriyasu Ando, Akira Tanimoto, Yasuo Takemoto
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Patent number: 5969706Abstract: An information retrieval apparatus includes a display section for displaying a first image; an enlargement section for continuously enlarging the first image displayed by the display section in response to an instruction of the user; and a determination section for determining that a magnification ratio of the first image enlarged by the enlargement section has reached a prescribed value. When the magnification ratio is determined to have reached the prescribed value, the display section displays at least one second image at a position related to the first image. When the first image is still enlarged by the enlargement section, the enlargement section enlarges the at least one second image at a magnification ratio equal to the magnification ratio used for enlarging the first image.Type: GrantFiled: October 15, 1996Date of Patent: October 19, 1999Assignee: Sharp Kabushiki KaishaInventors: Akira Tanimoto, Toshiyuki Masui
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Patent number: 5844561Abstract: The information search apparatus of the invention includes: a memory for storing character information therein, a display tablet having a function of displaying at least one character information and a function of inputting data, a detecting section for detecting a position at which an input pen has come into contact with the display tablet, and a control section for performing a control such that a function cursor, used for searching for arbitrary character information through the character information, is displayed at the detected position. In the information search apparatus, the control section extracts a plurality of character information from the character information for searching for the arbitrary character information through the character information.Type: GrantFiled: October 23, 1996Date of Patent: December 1, 1998Assignee: Sharp Kabushiki KaishaInventors: Akira Tanimoto, Toshiyuki Masui
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Patent number: 5021892Abstract: An image processing device for controlling data transfer includes an image scanner, an image printer, a facsimile control unit, bus lines for data transfer, a bidirectional parallel interface unit, and a main CPU in a housing. The device is connected to an external data processing device through the parallel interface unit. In addition to the functions which are obtained independent from the external data processing device, the image processing device realizes various kinds of functions by controlling the image scanner, the image printer facsimile control unit and the interface unit by the main CPU in response to commands from the data processing device. As a result, various kinds of image processing functions are carried out.Type: GrantFiled: December 26, 1989Date of Patent: June 4, 1991Assignee: Sharp Kabushiki KaishaInventors: Toshiro Kita, Susumu Genba, Masato Takemoto, Takashi Tatsumi, Toshiyuki Itoga, Yutaka Iizuka, Satoshi Tominaga, Mikio Higashiyama, Akira Tanimoto, Shinji Okamoto, Toshihiko Yoshida