Patents by Inventor Akira Ueda

Akira Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090192770
    Abstract: An analysis supporting apparatus that supports a product analyzing operation includes a model-data generating unit that generates model data regarding an analysis model of an analysis target component in association with component hierarchy data representing a hierarchy of components forming an analysis target product; a model-data updating unit that reflects results of an analyzing process in the model data; and a calorific-value summing unit that sums analysis information regarding the analysis target product based on the model data stored in associated with the component hierarchy data.
    Type: Application
    Filed: September 22, 2008
    Publication date: July 30, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Akira Ueda, Junichi Ishimine
  • Publication number: 20090192971
    Abstract: An analysis supporting apparatus that supports a product analyzing operation, includes a model-data generating unit that generates model data regarding an analysis model of an analysis target component in association with component hierarchy data representing a hierarchy of components forming an analysis target product; a model-data updating unit that reflects results of an analyzing process in the model data; and a simplified-model generating unit that generates, based on a rule registered in advance, simplified model data from the model data in which the results of the analyzing process have been reflected by the model-data updating unit.
    Type: Application
    Filed: September 18, 2008
    Publication date: July 30, 2009
    Applicant: Fujitsu Limited
    Inventors: Akira Ueda, Junichi Ishimine
  • Publication number: 20090192959
    Abstract: An analysis supporting apparatus that supports a product analyzing operation, includes a model-data generating unit that generates model data regarding an analysis model of an analysis target component in association with component hierarchy data representing a hierarchy of components forming an analysis target product, and a advice-data generating unit that generates, based on a logic registered in advance, advice data from the model data to improve design with respect to the analysis target product.
    Type: Application
    Filed: September 23, 2008
    Publication date: July 30, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Akira Ueda, Hideharu Matsushita, Junichi Ishimine
  • Publication number: 20090187903
    Abstract: A virtual multiprocessor system which does not require a memory apparatus for debugging includes: a physical processor, storage units for storing status information indicating respective statuses of logic processors, a dispatch unit which assigns one of the logic processors by switching the logic processors with respect to a physical processor, and an interrupt unit which suspends the processing currently executed by a current logic processor among the logic processors by issuing a debug interrupt request to the current logic processor; in the virtual multiprocessor system, the dispatch unit stores status information corresponding to the current logic processor into one of the storage units in response to the debug interrupt request issued to the current logic processor that is assigned to the physical processor.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 23, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Akira UEDA, Takao YAMAMOTO, Shinji OZAKI, Masahide KAKEDA
  • Patent number: 7548410
    Abstract: A capacitor has a capacitor element, a packaging material, and a sealing material. The capacitor element has an anode foil coupled to an anode terminal, a cathode foil coupled to a cathode terminal, a separator, and an electrolyte layer. The anode foil, the cathode foil and the separator are rolled together. The separator is between the anode foil and the cathode foil. The electrolyte layer is formed between the anode foil and the cathode foil. The packaging material has an opening and packages the capacitor element. The sealing material has a through hole where the anode terminal and the cathode terminal pass through and seals the opening of the packaging material. A given space is provided between the sealing material and the capacitor element. A stopper for securing the space is provided on at least one of the anode terminal and the cathode terminal.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: June 16, 2009
    Assignee: Nichicon Corporation
    Inventors: Akira Ueda, Ichirou Yamaji, Katsuharu Yamada, Minoru Funahashi, Junkichi Mabe, Ryoichi Kozaki
  • Patent number: 7533251
    Abstract: When a call instruction or interrupt branch is executed by a CPU, its return address is pushed to a stack memory. When a return instruction is executed, the pushed return address is popped from the stack memory. When a return instruction is executed by the CPU, a comparator compares the branch address output from the CPU and the address output from the stack memory. As a result of the comparison, if the addresses match, the branch address is not output as trace information. If the addresses do not match, the address register receives the branch address from the CPU and outputs the received branch address as the trace information.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: May 12, 2009
    Assignee: Panasonic Corporation
    Inventors: Atsushi Ubukata, Akira Ueda, Shigeyoshi Oda
  • Patent number: 7472310
    Abstract: The present invention aims at providing a debugging mechanism capable of detecting erroneous read access to a bus slave caused by a synchronization control infringement between bus masters due to a failure of software. Each of a dirty detector and a coherency error detector is used as a detector for monitoring a bus control unit and, during a period that write access corresponding to optionally designated conditions is present on a write buffer, detecting read access corresponding to conditions equal to the aforementioned conditions. A bus master includes a debugging unit. The debugging unit receives a coherency error notification from the coherency error detector to generate a debugging event, breaks an operation of the bus master, and performs various debugging operations while using the debugging event as a trigger.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 30, 2008
    Assignee: Panasonic Corporation
    Inventor: Akira Ueda
  • Publication number: 20080300832
    Abstract: A design/analysis linkage system performs the processing of recording, in a conversion information file, a conversion process in which design data is converted into a design information file suitable to making a model; of linking the aforementioned design information file with an analysis information file generated from the design information file for building up an analysis model; and of automatically reflecting in the design information file changes that have been made to the analysis information file during the analysis process.
    Type: Application
    Filed: July 25, 2008
    Publication date: December 4, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Akira UEDA
  • Publication number: 20080232034
    Abstract: A method of manufacturing a solid electrolytic capacitor includes: rolling an anode foil, a cathode foil and a separator together, the separator being a mixed fiber composed of a chemical fiber and a natural fiber and being between the anode foil and the cathode foil; degrading and removing the natural fiber with enzyme; and forming an electrolytic layer composed of solid polymer between the anode foil and the cathode foil after degrading and removing the natural fiber.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 25, 2008
    Applicant: FUJITSU MEDIA DEVICES LIMITED
    Inventors: Minoru FUNAHASHI, Akira UEDA, Katsuharu YAMADA
  • Patent number: 7417844
    Abstract: A stacked solid electrolytic capacitor has an anode foil composed of a valve metal, a cathode foil having carbon grains that are evaporated or physically adhered to a surface thereof, a separator and a solid electrolytic layer composed of a conducting polymer. The anode foil, the separator and the cathode foil are stacked in order. The solid electrolytic layer is formed between the anode foil and the cathode foil.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: August 26, 2008
    Assignee: Fujitsu Media Devices Limited
    Inventors: Hidetoshi Ishizuka, Toshiyuki Mizutani, Minoru Funahashi, Akira Ueda, Katsuharu Yamada, Kenya Sakurai
  • Publication number: 20080201120
    Abstract: An analysis support system has an analysis purpose input section being able to input an analysis purpose, an analysis level designator designating an analysis level representing a range for analysis according to the inputted analysis purpose, a configuration information record section recording configuration information about other component to be combined with each component, in association with the analysis level, a purpose-specific component group generator generating a purpose-specific component group representing an analytic component that is to configure the purpose-specific analytic model on the basis of the analysis level and the configuration information, and an analytic model generator generating the purpose-specific analytic model on the basis of a basic analytic model having the analytic component corresponding to the analysis object and the purpose-specific component group. An analytic model according to an analysis purpose can be readily generated, which improves the serviceability.
    Type: Application
    Filed: December 20, 2007
    Publication date: August 21, 2008
    Applicant: Fujitsu Limited
    Inventors: Hideharu MATSUSHITA, Akira Ueda
  • Patent number: 7405838
    Abstract: In a print system, where whole processing to generate final print data is carried out at a server, concentrated requests from many and unspecified clients, being the feature of Web communication, will increase the load on the server. For overcoming it, it is made feasible to distribute data necessary for generation of chit print data by overlay processing, from the server to a client or to a print server and execute the overlay processing at the client or at the print server to generate the chit print data.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: July 29, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Ueda, Tsunehiro Tsukada
  • Patent number: 7396606
    Abstract: A fuel-cell evaluation equipment includes a gas passageway for supplying gas to a fuel cell and a thermostat adapted to accommodate the fuel cell, wherein the gas passageway includes a first temperature regulator adapted to regulate the temperature of gas and a humidity regulator adapted to regulate the humidity of the gas. A thermostatic chamber of the thermostat regulates an inner temperature in the chamber according to a test condition. The thermostatic chamber is provided with a second temperature regulator into which gas flowing in the gas passageway flows. The gas flowing in the gas passageway is supplied to the fuel cell after heat exchange by the second temperature regulator.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: July 8, 2008
    Assignee: Espec Corp.
    Inventors: Hideki Tanaka, Kimio Yoshizumi, Hitoshi Ando, Akira Mizugaki, Hiroshi Okuda, Akira Ueda
  • Publication number: 20080082947
    Abstract: A circuit information acquisition and conversion device, a method, and a program therefor for acquiring a layer configuration, wire traces and shapes of via holes from circuit board design information; optimizing, before conversion into an analysis model, the output target range of the via holes on the basis of a package area, heat density distribution, and power consumption; and creating an analysis model that is suitable for a purpose of the analysis are provided.
    Type: Application
    Filed: February 15, 2007
    Publication date: April 3, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Akira Ueda, Hideharu Matsushita
  • Publication number: 20080043403
    Abstract: A capacitor has a capacitor element, a packaging material, and a sealing material. The capacitor element has an anode foil coupled to an anode terminal, a cathode foil coupled to a cathode terminal, a separator, and an electrolyte layer. The anode foil, the cathode foil and the separator are rolled together. The separator is between the anode foil and the cathode foil. The electrolyte layer is formed between the anode foil and the cathode foil. The packaging material has an opening and packages the capacitor element. The sealing material has a through hole where the anode terminal and the cathode terminal pass through and seals the opening of the packaging material. A given space is provided between the sealing material and the capacitor element. A stopper for securing the space is provided on at least one of the anode terminal and the cathode terminal.
    Type: Application
    Filed: January 11, 2007
    Publication date: February 21, 2008
    Inventors: Akira Ueda, Ichirou Yamaji, Katsuharu Yamada, Minoru Funahashi, Junkichi Mabe, Ryoichi Kozaki
  • Patent number: 7312979
    Abstract: A stacked solid electrolytic capacitor has a substrate, a capacitor element, and a metal cap. The substrate has electrical conductivity. The capacitor element is provided on the substrate. The metal cap is coupled to the substrate, covers the capacitor element and is electrically conducted to the substrate. A cathode of the capacitor element is electrically conducted to the substrate.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: December 25, 2007
    Assignee: Fujitsu Media Devices Limited
    Inventors: Hidetoshi Ishizuka, Minoru Funahashi, Toshiyuki Mizutani, Akira Ueda, Katsuharu Yamada
  • Publication number: 20070267773
    Abstract: The present invention provides a process for producing a thermoplastic resin sheet with controlled warpage, the process including extruding a thermoplastic resin sheet, while giving mechanically controlled warpage to the sheet at a position where a temperature of the sheet extruded becomes around a grass transition temperature (Tg) of a thermoplastic resin constituting the sheet. In this production process, the sheet is preferably allowed to pass through a pair of warpage-controlling upper and lower rolls at the position, and the mechanically controlled warpage is preferably given to the sheet by selecting shapes of the warpage-controlling rolls and/or by disposing the warpage-controlling rolls on an upper side or a lower side of a height where a flat sheet is obtained. According to this production process, a thermoplastic resin sheet with controlled warpage can be produced simply and easily with high efficiency.
    Type: Application
    Filed: April 18, 2007
    Publication date: November 22, 2007
    Inventors: Takehisa Kishimoto, Akira Ueda
  • Publication number: 20070171598
    Abstract: A stacked solid electrolytic capacitor has a substrate, a capacitor element, and a metal cap. The substrate has electrical conductivity. The capacitor element is provided on the substrate. The metal cap is coupled to the substrate, covers the capacitor element and is electrically conducted to the substrate. A cathode of the capacitor element is electrically conducted to the substrate.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 26, 2007
    Inventors: Hidetoshi Ishizuka, Minoru Funahashi, Toshiyuki Mizutani, Akira Ueda, Katsuharu Yamada
  • Publication number: 20070104961
    Abstract: The present invention provides a functional thermoplastic resin sheet including a thin film of at least one layer formed on at least one side of a thermoplastic resin sheet by a transfer method, wherein at least one layer of the thin film has functionality. The functional thermoplastic resin sheet of the first invention has a thin film of at least one layer formed on an uneven surface of a thermoplastic resin sheet having the uneven surface by a transfer method. The production process includes transferring, using a transfer film with a thin film of at least one layer formed on a surface of a base film, the thin film to an uneven surface of a thermoplastic resin sheet having the uneven surface, at which when the glass transition temperature of a thermoplastic resin sheet is denoted as Tg, a surface temperature of the thermoplastic resin sheet is in a range of not lower than (Tg?10° C.) and not higher than (Tg+70° C.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 10, 2007
    Inventors: Toshio Awaji, Naofumi Tsujino, Kazuhisa Hirata, Takehisa Kishimoto, Akira Ueda, Junichiro Nakagawa, Michio Matsuura
  • Patent number: D579758
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: November 4, 2008
    Assignee: YKK AP Inc.
    Inventors: Hideoki Tanaka, Naoki Yasuda, Yutaka Nakamura, Toshio Isono, Michizumi Ito, Yasuhito Hibi, Yoshitada Sakamoto, Masaki Nomura, Akira Ueda