Patents by Inventor Akira Yamaga
Akira Yamaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420052Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: September 13, 2023Publication date: December 28, 2023Inventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Patent number: 11804267Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: GrantFiled: June 29, 2022Date of Patent: October 31, 2023Assignee: Kioxia CorporationInventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
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Publication number: 20220328103Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Patent number: 11410732Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: GrantFiled: March 9, 2021Date of Patent: August 9, 2022Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
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Publication number: 20210193228Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: March 9, 2021Publication date: June 24, 2021Inventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Patent number: 10978157Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: GrantFiled: February 14, 2020Date of Patent: April 13, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
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Publication number: 20200185036Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: February 14, 2020Publication date: June 11, 2020Inventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Patent number: 10600485Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: GrantFiled: March 15, 2019Date of Patent: March 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
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Patent number: 10574272Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.Type: GrantFiled: March 1, 2018Date of Patent: February 25, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuta Kumano, Kazumasa Yamamoto, Hironori Uchikawa, Akira Yamaga
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Publication number: 20190214090Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: March 15, 2019Publication date: July 11, 2019Inventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Patent number: 10276243Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: GrantFiled: January 22, 2018Date of Patent: April 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
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Publication number: 20190089384Abstract: A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.Type: ApplicationFiled: March 1, 2018Publication date: March 21, 2019Inventors: Yuta KUMANO, Kazumasa YAMAMOTO, Hironori UCHIKAWA, Akira YAMAGA
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Patent number: 10089241Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.Type: GrantFiled: September 12, 2016Date of Patent: October 2, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tokumasa Hara, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
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Patent number: 10061691Abstract: According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The controller writes second processed data acquired by a second process into the nonvolatile memory during a second period. The first process is for the purpose of improving the endurance of memory cells. The second process is for the purpose of decreasing inter-cell interferences between adjacent cells.Type: GrantFiled: March 15, 2017Date of Patent: August 28, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kejen Lin, Tokumasa Hara, Hironori Uchikawa, Juan Shi, Akira Yamaga, Sho Kodama, Keiri Nakanishi
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Publication number: 20180144801Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: January 22, 2018Publication date: May 24, 2018Applicant: Toshiba Memory CorporationInventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Publication number: 20180068719Abstract: According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The controller writes second processed data acquired by a second process into the nonvolatile memory during a second period. The first process is for the purpose of improving the endurance of memory cells. The second process is for the purpose of decreasing inter-cell interferences between adjacent cells.Type: ApplicationFiled: March 15, 2017Publication date: March 8, 2018Applicant: Toshiba Memory CorporationInventors: Kejen LIN, Tokumasa HARA, Hironori UCHIKAWA, Juan SHI, Akira YAMAGA, Sho KODAMA, Keiri NAKANISHI
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Patent number: 9911498Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: GrantFiled: May 5, 2017Date of Patent: March 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga
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Publication number: 20170262379Abstract: According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.Type: ApplicationFiled: September 12, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Tokumasa HARA, Osamu Torii, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda, Juan Shi, Hironori Uchikawa, Kejen Lin, Akira Yamaga
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Publication number: 20170243657Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: May 5, 2017Publication date: August 24, 2017Inventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Patent number: 9721666Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: GrantFiled: June 6, 2016Date of Patent: August 1, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu Shirakawa, Kenta Yasufuku, Akira Yamaga