Patents by Inventor Akira Yamaga
Akira Yamaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170076801Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.Type: ApplicationFiled: June 6, 2016Publication date: March 16, 2017Inventors: Masanobu SHIRAKAWA, Kenta YASUFUKU, Akira YAMAGA
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Patent number: 9264070Abstract: A memory controller includes a memory interface that has multiple channels and carries out writing into a nonvolatile memory through each of the channels, a data buffer, an ECC (error correcting code) encoder for applying an error correction encoding processing on write data which are to be written into the nonvolatile memory to generate ECC data, a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory, a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder, and a channel scheduler for transferring the write data stored in the data buffer and the ECC data to the channels of the memory interface as allocated by the channel allocation part.Type: GrantFiled: November 26, 2012Date of Patent: February 16, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuhiro Suzumura, Akira Yamaga
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Patent number: 8879349Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.Type: GrantFiled: August 6, 2013Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenichiro Yoshii, Ikuo Magaki, Naoto Oshiyama, Tokumasa Hara, Akira Yamaga, Ryo Yamaki, Kenta Yasufuku, Naomi Takeda, Yu Nakanishi, Arata Miyamoto, Naoaki Kokubun, Daisuke Iwai
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Publication number: 20140241096Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.Type: ApplicationFiled: August 6, 2013Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kenichiro YOSHII, Ikuo MAGAKI, Naoto OSHIYAMA, Tokumasa HARA, Akira YAMAGA, Ryo YAMAKI, Kenta YASUFUKU, Naomi TAKEDA, Yu NAKANISHI, Arata MIYAMOTO, Naoaki KOKUBUN, Daisuke IWAI
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Patent number: 8812774Abstract: According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.Type: GrantFiled: August 25, 2011Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Shinichi Kanno, Kazuhiro Fukutomi, Akira Yamaga
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Patent number: 8751896Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).Type: GrantFiled: July 11, 2013Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Akira Yamaga
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Publication number: 20140068378Abstract: According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.Type: ApplicationFiled: February 21, 2013Publication date: March 6, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kenichiro YOSHII, Naoaki Kokubun, Naoto Oshiyama, Ryo Yamaki, Ikuo Magaki, Kenta Yasufuku, Akira Yamaga
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Publication number: 20130297984Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).Type: ApplicationFiled: July 11, 2013Publication date: November 7, 2013Inventor: Akira Yamaga
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Patent number: 8499216Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).Type: GrantFiled: January 17, 2013Date of Patent: July 30, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Akira Yamaga
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Publication number: 20130173997Abstract: A memory controller includes a memory interface that has multiple channels and carries out writing into a nonvolatile memory through each of the channels, a data buffer, an ECC (error correcting code) encoder for applying an error correction encoding processing on write data which are to be written into the nonvolatile memory to generate ECC data, a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory, a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder, and a channel scheduler for transferring the write data stored in the data buffer and the ECC data to the channels of the memory interface as allocated by the channel allocation part.Type: ApplicationFiled: November 26, 2012Publication date: July 4, 2013Inventors: Tatsuhiro SUZUMURA, Akira Yamaga
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Patent number: 8418028Abstract: To provide a Chien search device and a Chien search method capable of performing a Chien search process at a high speed. The Chien search device calculates an error position at the time of correcting an error included in data read from a nonvolatile memory, and includes a first processing unit that performs a search process of an error position in at least one-bit unit to an error-correction area of input data, and a second processing unit that processes at one time plural bits in an non-error-correction-target area of the input data.Type: GrantFiled: September 19, 2008Date of Patent: April 9, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Akira Yamaga
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Patent number: 8381066Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).Type: GrantFiled: December 22, 2011Date of Patent: February 19, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Akira Yamaga
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Patent number: 8312348Abstract: An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error.Type: GrantFiled: February 27, 2009Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Akira Yamaga
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Publication number: 20120246383Abstract: According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.Type: ApplicationFiled: August 25, 2011Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Shigehiro Asano, Shinichi Kanno, Kazuhiro Fukutomi, Akira Yamaga
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Publication number: 20120166908Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).Type: ApplicationFiled: December 22, 2011Publication date: June 28, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Akira Yamaga
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Patent number: 8176389Abstract: A decoder device includes: a decoder that decodes data stored in a storage medium by performing error correction on the data, the error correction being capable of correcting code error and code erasure included in the data; a memory that stores a history of an address in the storage medium of a code included in the data, the code being detected to have the code error by the decoding unit; and a controller that controls the decoder to change a detail of the error correction based on the history stored in the memory.Type: GrantFiled: June 3, 2008Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Koji Horisaki, Akira Yamaga
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Patent number: 8086933Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).Type: GrantFiled: September 19, 2008Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Akira Yamaga
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Publication number: 20110047441Abstract: To provide a Chien search device and a Chien search method capable of performing a Chien search process at a high speed. The Chien search device calculates an error position at the time of correcting an error included in data read from a nonvolatile memory, and includes a first processing unit that performs a search process of an error position in at least one-bit unit to an error-correction area of input data, and a second processing unit that processes at one time plural bits in an non-error-correction-target area of the input data.Type: ApplicationFiled: September 19, 2008Publication date: February 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Akira Yamaga
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Publication number: 20100313099Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).Type: ApplicationFiled: September 19, 2008Publication date: December 9, 2010Applicant: Kabushiki Kaisha ToshibaInventor: Akira Yamaga
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Publication number: 20090222708Abstract: An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error.Type: ApplicationFiled: February 27, 2009Publication date: September 3, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Akira YAMAGA