Abstract: A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units.

Abstract: A data processing apparatus, including a number of electronic circuit units, in which high-speed data can be transmitted among the electronic circuit units. When data is transmitted from one electronic circuit unit to another electronic circuit unit, a clock signal to fetch the data in the sink side electronic circuit unit is transmitted from the source side electronic circuit unit via a clock signal line having the same signal propagation delay characteristics as those of the data signal line.

Abstract: A cooling apparatus for electronic equipment for improving the reliability of the equipment by making uniform the temperature distribution of heat generating devices mounted on the electronic equipment, more particularly on a computer and for reducing the working process required at the time of performing a maintenance of a printed circuit board in the electronic equipment by stacking, in a frame, the electronic printed circuit boards on which the heat generating devices, such as a CPU and memories, are mounted at predetermined intervals. The cooling apparatus has a fan fastened to one wall surface of a chamber and a plurality of jet cooling devices formed on the surface opposing the wall surface. The jet cooling devices are formed in parallel to the printed circuit boards. The jet cooling devices are slits, or nozzles or jet stream ducts extending among the printed circuit boards and are so formed as to supply cooling air in a jet stream state to each heat generating device.

Abstract: A cooling apparatus for an electronic device of high calorific density including an elastomer interposed between a semiconductor chip and a heat sink so as to connect them thermally. The elastomer may also be in close contact with a large number of semiconductor chips having various configurations which are mounted on a board, so that the elastomer is thermally connected with them, whereby the elastomer absorbs thermal deformations.

Abstract: In a cooling apparatus of an electronic equipment, a plurality each of integrated circuit devices and large-scale integrated circuit devices are mounted onto a plurality of substrates, respectively, and a cooling fan supplies cooling air from outside to each of these integrated circuit devices. A duct having a comb-tooth shape suitable for encompassing each substrate and defining flow paths along the substrates introduces the cooling air supplied by the cooling fan to each of the integrated circuit devices. The duct includes a plurality of small holes disposed at positions corresponding to the positions of the integrated circuit devices on the substrates and having open areas corresponding to the heating values of the integrated circuit devices. The small holes flow the cooling air supplied by the cooling fan as jet streams to the integrated circuit devices. This jet stream cooling improves cooling performance and can make uniform the temperature distribution of the integrated circuit devices.

Abstract: A semiconductor apparatus comprises a heat diffusing plate and a surface installing printed board. A semiconductor device of a high heat generation is installed on the heat diffusing plate. A surface installing package and chip parts are installed on both surfaces of the printed board. A through hole is formed at the center of the printed board so that the semiconductor device is located at the center. The heat diffusing plate on which the semiconductor device has been installed and the surface installing printed board are connected and integrated.

Abstract: An LSI cooling apparatus having various structures is used in electronic devices such as computer systems. In particular, the LSI cooling of apparatus is suitable for cooling of LSIs having high heat generating densities. In a cooling apparatus of the present invention, a heat sink is constructed to be small in pressure loss and excellent in cooling performance. This is because the heat sink comprises thin wire fins so set that the Reynold's number may not exceed 40. As a result, LSIs generating a large amount of heat can be cooled. Further, a heat sink having rigidity can be obtained by disposing wide-width wire drawn substances in thin wires or by using supports. Further, a computer comprising LSIs equipped with heat sinks can cope with various cooling air sending methods and it can be cooled with low noises.

Abstract: A method for wiring a power supply for a large-scale integrated circuit. The power supply wires define a power supply grid surrounding lattice openings with fixed longitudinal and transverse lattice dimensions. The wire width is determined based on the integrated circuit chip size, the number of function circuits to be on the integrated circuit, the electrical power requirements of the function circuits, and the fixed longitudinal and transverse lattice dimensions. Longitudinal and transverse locations of the power supply wires chips are determined based on the determined wire width and the fixed longitudinal and transverse dimensions of the lattice openings. Alternatively, the wire width may be fixed and the dimensions of the lattice openings determined based on the integrated circuit chip size, the number of function circuits, the electrical power requirements of the function circuits and that wire width.

Abstract: This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted.

Abstract: A spindle driving device for a covering machine includes a plurality of groups of spindles. Each group of spindles includes a predetermined number of spindles and an electric motor is associated with each group. A driving pulley is removably installed on each motor and a tension pulley is associated with each group of spindles. An endless belt is stretched around the driving pulley, the spindle wharves attached to each spindle and the tension pulley in each group. The tension pulley is mounted at a central portion of an arm and the arm is supported at one end by a pivot which is connected to a slider for movement along a guide-rod for removing slackness in the endless belt. The other end of the arm is attached to an energizing member for biasing the arm in a direction for removing slackness in the endless belt.

Abstract: Multi-phase clock signals are delivered to a large number of load circuits scattered on a chip from clock signal input pins through at least three stage buffer circuits. The first stage buffer circuits are arranged in the neighborhood of the input pins, and the second stage buffer circuits are arranged on the central portion of the chip. Equivalent-length wirings are made between the successive two stage buffer circuits and the same number of subsequent stage buffer circuit are connected with each of certain stage buffer circuits for the respective phases so as to provide equal resistances and equal capacitances. Equivalent-length wirings are also made between final stage buffer circuits and the corresponding load circuits, and the same number of load circuits are connected with each final stage buffer circuit. Thus, equal delay times are provided in the clock signal paths from the input pins to the load circuits at the respective phases.

Abstract: A logic circuit (FIGS. 4A, 5A and 6A) comprises a current switch circuit (FIG. 4A) which has a non-threshold transfer characteristic (FIG. 4B), operates in non-saturation region, and is suited to a high speed operation.The current switch circuit is formed by a pair of transistors (6 or 7, and 8), one of which (6 or 7) receives an input signal at its base, and the other (8) has its base and collector connected in d.c. coupling to each other. The pair of transistors are connected with a common constant current source (9) at their emitters, deliver an output from their collectors, and are so biased as to operate in the non-saturation region.In the current switch circuit, due to the d.c. coupling between the base and the collector of the other transistor (8), the voltage level of the collector changes linearly in accordance with the input signal of the current switch circuit. This allows for a transfer characteristic having no threshold and a very small delay time between the input signal and the output signal.

Abstract: In a logic circuit comprising a low-amplitude CML circuit including a transistor functioning as a constant-current source, the constant-current source transistor is biased by a bias power source which is capable of compensating for both the power supply voltage dependency and the junction temperature dependency of the CML circuit. In the logic circuit, negative feedback is applied to the constant-current source transistor through its base bias circuit to compensate for the dependency of the constant-current source transistor on the power supply voltage, and the difference between the junction temperature dependency of the junction voltage of one of two transistors in the control circuit and that of the other transistor due to the different emitter current densities is utilized to compensate for the dependency of the constant current source transistor on the junction temperature.

Abstract: A current mode logic circuit (CML) consisting of emitter-coupled transistors, one acting as a reference element and the other as an input element, a regulation transistor for regulating the emitter current of the transistors, a biasing circuit composed of a diode, a Schottky diode and a resistance element connected in series between a V.sub.EE terminal and a V.sub.CC terminal and a biasing transistor, the collector of the biasing transistor being connected through a resistor to V.sub.CC and connected to the base of the reference transistor, the emitter of which being connected through a resistor to V.sub.