Patents by Inventor Akira Yoshio
Akira Yoshio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080220136Abstract: To provide a method for manufacturing, etc., dried foods that can be cooked or reconstituted in hot water in a short time and have a good texture and a good unraveling property. [Solution Means] A dried food is manufactured by subjecting a to-be-processed object, obtained by shaping a prepared object of a raw material containing starchy matter to a predetermined shape, to at least: (1) a first step P1 of performing a boiling treatment; (2) a second step P2 of putting the boiled to-be-processed object in contact with an aqueous solution after the abovementioned first step P1; and (3) a third step P3 of subjecting the to-be-processed object, subjected to the abovementioned second step P2, to a wind drying treatment at conditions of a temperature of 45 to 100° C. and a humidity of 5 to less than 55%.Type: ApplicationFiled: December 22, 2004Publication date: September 11, 2008Applicant: YAMADAI CORPORATIONInventors: Keiichi Ookubo, Nobuaki Matsuzawa, Akira Yoshio
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Publication number: 20070284247Abstract: A contrivance is applied to the wiring configuration for securely feeding electricity to electrodes provided in a multiplicity of reaction regions arranged on a substrate, irrespectively of the arrangement configuration of the electrodes. A bioassay substrate being a disk-shaped substrate having such a configuration that reaction regions 2 to be fields for interactions between substances are arranged in multiplicity and electrodes E are provided in the reaction regions 2, wherein feeder wirings 401, 402 which are extended from a current passing portion or portions (for example, 36) provided at a central portion of the substrate 1 and which are connected to the electrodes E1, E2 in the reaction regions 2 are extended to entirely cover the whole area of the substrate.Type: ApplicationFiled: November 11, 2004Publication date: December 13, 2007Inventor: Akira Yoshio
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Patent number: 7232760Abstract: A method for producing a semiconductor device, polishing method, and polishing apparatus, suppressing occurrence of dishing and erosion in a flattening process by polishing of a metal film for constituting an interconnection of a semiconductor device having a multilayer interconnection structure. The production method includes the steps of: forming a passivation film exhibiting an action of inhibiting an electrolytic reaction of a metal at the surface of the metal film; selectively removing the passivation film on a projecting portion so as to expose the projecting portion of the metal film at the surface; removing the exposed projecting portion of the metal film by electrolytic polishing so as to flatten unevenness of the surface of the metal film; and removing the metal film present on an insulation film from the metal film with the flattened surface by electrolytic composite polishing combining electrolytic polishing and mechanical polishing so as to form an interconnection.Type: GrantFiled: January 20, 2004Date of Patent: June 19, 2007Assignee: Sony CorporationInventors: Takeshi Nogami, Akira Yoshio, Shuzo Sato
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Publication number: 20070077644Abstract: Provided is a configuration of feeder wirings for electrodes provided for reaction regions arranged in multiplicity on a disk-shaped substrate. Feeder wirings extended from a current passing portion (U) provided at a central portion of a substrate (A) to electrodes provided in reaction regions (R) arranged in multiplicity on the substrate so as to be fields for interactions between substances are each composed of a first wiring (1) led out from the current passing portion (U) toward the outer circumference of the substrate, a second wiring (2) branched from the first wiring, and a third wiring (3) branched further from the second wiring, and a voltage is impressed on the electrodes from the current passing portion (U) through the feeding wirings (1, 2, 3), to develop an electric field in the reaction regions (R).Type: ApplicationFiled: October 21, 2004Publication date: April 5, 2007Inventor: Akira Yoshio
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Publication number: 20070051632Abstract: A polishing method and polishing apparatus able to easily flatten an initial unevenness with an excellent efficiency of removal of excess copper film and suppress damage to a lower interlayer insulation film, and a plating method and plating apparatus able to deposit a flat copper film. The polishing method comprises the steps of measuring thickness equivalent data of a film on a wafer, making a cathode member smaller than the surface face a region thereof, interposing an electrolytic solution between the surface and the cathode member, applying a voltage using the cathode member as a cathode and the film an anode, performing electrolytic polishing by electrolytic elution or anodic oxidation and chelation and removal of a chelate film in the same region preferentially from projecting portions of the film until removing the target amount of film obtained from the thickness equivalent data, and repeating steps of moving the cathode member to another region to flattening the regions over the entire surface.Type: ApplicationFiled: October 31, 2006Publication date: March 8, 2007Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
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Patent number: 7186322Abstract: A method of production and a method of polishing a semiconductor device and a polishing apparatus, capable of easily flattening an initial unevenness of a metal film, excellent in efficiency of removal of an excess metal film, and capable of suppressing damage to an interlayer insulation film below the metal film when flattening the metal film by polishing, the polishing method including the steps of interposing an electrolytic solution including a chelating agent between a cathode member and the copper film, applying a voltage between the cathode member used as a cathode and the copper film used as an anode to oxidize the surface of the copper film and forming a chelate film of the oxidized copper, selectively removing a projecting portion of the chelate film corresponding to the shape of the copper film to expose the projecting portion of the copper film at its surface, and repeating the above chelate film forming step and the above chelate film removing step until the projecting portion of the copper filmType: GrantFiled: December 26, 2002Date of Patent: March 6, 2007Assignee: Sony CorporationInventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Hiizu Ootorii, Zenya Yasuda, Masao Ishihara, Takeshi Nogami, Naoki Komai
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Publication number: 20060127904Abstract: The present invention provides a hybridization detector (1a) and the like that are improved in the hybridization efficiency by arraying nucleotide probes in a stretched form, a sensor chip including the hybridization detector (1a) or the like, and a method of hybridization using these detectors or the chip. The hybridization detector (la) and the like include a reaction region (R) for hybridization between the nucleotide probes (X) and target nucleotide sequences (Y) having a base sequence complementary to the nucleotide probes (X). The reaction region (R) has a configuration for stretching the nucleotide probes (X) by an electric field and immobilizing the nucleotide probes (X) on ends (E) of scanning electrodes (C) by dielectrophoresis.Type: ApplicationFiled: August 20, 2003Publication date: June 15, 2006Inventors: Yuji Segawa, Takayoshi Mamine, Yasuhiro Sakamoto, Akira Yoshio, Takuro Yamamoto
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Publication number: 20050112548Abstract: Disclosed herein is a unit for detecting an interaction between substances, including a reaction region for providing sites for the interaction between the substances, at least one pair of opposite electrodes disposed oppositely to each other so as to make it possible to impress an electric field on a medium contained in the reaction region, and an injection hole and an exhaust hole for feeding the medium containing the substances into the reaction region by capillarity.Type: ApplicationFiled: September 30, 2004Publication date: May 26, 2005Inventors: Yuji Segawa, Akira Yoshio
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Patent number: 6855634Abstract: A polishing method able to easily flatten unevenness formed on the surface of a film to be polished and able to efficiently polish the film flat while suppressing damage to an interlayer insulating film below the film, comprising, when polishing an object having a film such as an interconnection layer formed burying interconnection grooves formed in an insulating film of a substrate, supplying a polishing solution over the surface to be polished at least substantially parallel to the surface to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the processing solution or arranging a cathode member facing the surface and supplying an electrolytic solution containing a chelating agent between the surface and cathode member while supplying voltage between the film and the cathode member to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the electrolytic solution, and a polishinType: GrantFiled: September 26, 2001Date of Patent: February 15, 2005Assignee: Sony CorporationInventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
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Publication number: 20050016960Abstract: A method for producing a semiconductor device, polishing method, and polishing apparatus, suppressing occurrence of dishing and erosion in a flattening process by polishing of a metal film for constituting an interconnection of a semiconductor device having a multilayer interconnection structure. The production method includes the steps of: forming a passivation film exhibiting an action of inhibiting an electrolytic reaction of a metal at the surface of the metal film; selectively removing the passivation film on a projecting portion so as to expose the projecting portion of the metal film at the surface; removing the exposed projecting portion of the metal film by electrolytic polishing so as to flatten unevenness of the surface of the metal film; and removing the metal film present on an insulation film from the metal film with the flattened surface by electrolytic composite polishing combining electrolytic polishing and mechanical polishing so as to form an interconnection.Type: ApplicationFiled: January 20, 2004Publication date: January 27, 2005Inventors: Takeshi Nogami, Akira Yoshio, Shuzo Sato
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Patent number: 6808617Abstract: A polishing method and polishing apparatus able to easily flatten an initial unevenness with an excellent efficiency of removal of excess copper film and suppress damage to a lower interlayer insulation film, and a plating method and plating apparatus able to deposit a flat copper film. The polishing method comprises the steps of measuring thickness equivalent data of a film on a wafer, making a cathode member smaller than the surface face a region thereof, interposing an electrolytic solution between the surface and the cathode member, applying a voltage using the cathode member as a cathode and the film an anode, performing electrolytic polishing by electrolytic elution or anodic oxidation and chelation and removal of a chelate film in the same region preferentially from projecting portions of the film until removing the target amount of film obtained from the thickness equivalent data, and repeating steps of moving the cathode member to another region to flattening the regions over the entire surface.Type: GrantFiled: September 19, 2001Date of Patent: October 26, 2004Assignee: Sony CorporationInventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
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Patent number: 6797623Abstract: A method of production and a method of polishing a semiconductor device and a polishing apparatus, capable of easily flattening an initial unevenness of a metal film, excellent in efficiency of removal of an excess metal film, and capable of suppressing damage to an interlayer insulation film below the metal film when flattening the metal film by polishing, the polishing method including the steps of interposing an electrolytic solution including a chelating agent between a cathode member and the copper film, applying a voltage between the cathode member used as a cathode and the copper film used as an anode to oxidize the surface of the copper film and forming a chelate film of the oxidized copper, selectively removing a projecting portion of the chelate film corresponding to the shape of the copper film to expose the projecting portion of the copper film at its surface, and repeating the above chelate film forming step and the above chelate film removing step until the projecting portion of the copper filmType: GrantFiled: March 8, 2001Date of Patent: September 28, 2004Assignee: Sony CorporationInventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Hiizu Ootorii, Zenya Yasuda, Masao Ishihara, Takeshi Nogami, Naoki Komai
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Publication number: 20040182720Abstract: A polishing method and polishing apparatus able to easily flatten an initial unevenness with an excellent efficiency of removal of excess copper film and suppress damage to a lower interlayer insulation film, and a plating method and plating apparatus able to deposit a flat copper film. The polishing method comprises the steps of measuring thickness equivalent data of a film on a wafer, making a cathode member smaller than the surface face a region thereof, interposing an electrolytic solution between the surface and the cathode member, applying a voltage using the cathode member as a cathode and the film an anode, performing electrolytic polishing by electrolytic elution or anodic oxidation and chelation and removal of a chelate film in the same region preferentially from projecting portions of the film until removing the target amount of film obtained from the thickness equivalent data, and repeating steps of moving the cathode member to another region to flattening the regions over the entire surface.Type: ApplicationFiled: January 27, 2004Publication date: September 23, 2004Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
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Publication number: 20040092110Abstract: A polishing method able to easily flatten unevenness formed on the surface of a film to be polished and able to efficiently polish the film flat while suppressing damage to an interlayer insulating film below the film, comprising, when polishing an object having a film such as an interconnection layer formed burying interconnection grooves formed in an insulating film of a substrate, supplying a polishing solution over the surface to be polished at least substantially parallel to the surface to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the processing solution or arranging a cathode member facing the surface and supplying an electrolytic solution containing a chelating agent between the surface and cathode member while supplying voltage between the film and the cathode member to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the electrolytic solution, and a polishinType: ApplicationFiled: October 29, 2003Publication date: May 13, 2004Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
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Patent number: 6693036Abstract: A method for producing a semiconductor device, polishing method, and polishing apparatus, suppressing occurrence of dishing and erosion in a flattening process by polishing of a metal film for constituting an interconnection of a semiconductor device having a multilayer interconnection structure. The production method includes the steps of: forming a passivation film exhibiting an action of inhibiting an electrolytic reaction of a metal at the surface of the metal film; selectively removing the passivation film on a projecting portion so as to expose the projecting portion of the metal film at the surface; removing the exposed projecting portion of the metal film by electrolytic polishing so as to flatten unevenness of the surface of the metal film; and removing the metal film present on an insulation film from the metal film with the flattened surface by electrolytic composite polishing combining electrolytic polishing and mechanical polishing so as to form an interconnection.Type: GrantFiled: September 6, 2000Date of Patent: February 17, 2004Assignee: Sony CorporationInventors: Takeshi Nogami, Akira Yoshio, Shuzo Sato
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Patent number: 6638564Abstract: A method of electroless plating for processing a plating surface to form a barrier layer being capable of uniformly forming a barrier layer and reducing the consumption of a processing solution, comprising a step of feeding a processing solution used in at least one of the pre-processing steps of the electroless plating and the electroless plating step to the plating surface for puddling treatment, or, using a processing solution at least containing, with respect to one mole of a first metallic material supplying a main ingredient of the barrier layer, three or more moles of a completing agent and three or more moles of reducing agent and having a pH value adjusted to 9 or more and stored in an atmosphere of an inert gas or ammonia gas, and a corresponding electroless plating apparatus.Type: GrantFiled: April 9, 2001Date of Patent: October 28, 2003Assignee: Sony CorporationInventors: Yuji Segawa, Akira Yoshio, Masatoshi Suzuki, Katsumi Watanabe, Shuzo Sato
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Publication number: 20030114004Abstract: A method of production and a method of polishing a semiconductor device and a polishing apparatus, capable of easily flattening an initial unevenness of a metal film, excellent in efficiency of removal of an excess metal film, and capable of suppressing damage to an interlayer insulation film below the metal film when flattening the metal film by polishing, the polishing method including the steps of interposing an electrolytic solution including a chelating agent between a cathode member and the copper film, applying a voltage between the cathode member used as a cathode and the copper film used as an anode to oxidize the surface of the copper film and forming a chelate film of the oxidized copper, selectively removing a projecting portion of the chelate film corresponding to the shape of the copper film to expose the projecting portion of the copper film at its surface, and repeating the above chelate film forming step and the above chelate film removing step until the projecting portion of the copper filmType: ApplicationFiled: December 26, 2002Publication date: June 19, 2003Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Hiizu Ootorii, Zenya Yasuda, Masao Ishihara, Takeshi Nogami, Naoki Komai
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Patent number: 6555158Abstract: There is a method and apparatus for plating in which electroless copper plating is performed in a contact hole and an interconnect trench on a minute scale of a semiconductor integrated circuit device, and a plating structure. Organic material originated from an organic gas carried over from the preceding step is removed from the inner surface of a blind hole, thereafter the surface of the barrier layer is subjected to predetermined pretreatments comprising a hydroxylation treatment, a coupling treatment, a Pd colloidal solution treatment and the like, and following the pretreatments, electroless plating with copper is effected desirably under influence of ultrasonic waves. Hence, a uniform, good quality plating layer is formed inside and outside the hole and a CMP processing following the plating is performed with ease.Type: GrantFiled: January 20, 2000Date of Patent: April 29, 2003Assignee: Sony CorporationInventors: Akira Yoshio, Yuji Segawa
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Patent number: 6534117Abstract: When a barrier layer formed on a surface of a contact hole is subjected to electroless plating of copper, a salt of a metal such as gold, nickel, palladium, cobalt or platinum is added as a plating accelerator in an amount of 1 mol % or less based on a copper salt in a composition of an electroless plating solution, whereby the metal having the higher catalytic activity than copper is precipitated before precipitation of copper, and copper can then be precipitated as a good-quality plated film.Type: GrantFiled: June 30, 2000Date of Patent: March 18, 2003Assignee: Sony CorporationInventors: Akira Yoshio, Yuji Segawa, Naoki Komai
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Publication number: 20020070126Abstract: A polishing method and polishing apparatus able to easily flatten an initial unevenness with an excellent efficiency of removal of excess copper film and suppress damage to a lower interlayer insulation film, and a plating method and plating apparatus able to deposit a flat copper film. The polishing method comprises the steps of measuring thickness equivalent data of a film on a wafer, making a cathode member smaller than the surface face a region thereof, interposing an electrolytic solution between the surface and the cathode member, applying a voltage using the cathode member as a cathode and the film an anode, performing electrolytic polishing by electrolytic elution or anodic oxidation and chelation and removal of a chelate film in the same region preferentially from projecting portions of the film until removing the target amount of film obtained from the thickness equivalent data, and repeating steps of moving the cathode member to another region to flattening the regions over the entire surface.Type: ApplicationFiled: September 19, 2001Publication date: June 13, 2002Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami