Patents by Inventor Akitaka Kimura

Akitaka Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6201823
    Abstract: A semiconductor device and method of forming a current block layer structure includes the steps of providing dielectric stripe masks defining at least a stripe-shaped opening on a surface of a compound semiconductor region having a hexagonal crystal structure, and selectively growing at least a current block layer of a compound semiconductor having the hexagonal crystal structure on the surface of the compound semiconductor region by use of the dielectric stripe masks.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: March 13, 2001
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Masaaki Nido
  • Patent number: 6100106
    Abstract: A process for producing a semiconductor light-emitting device, which comprises forming, on a substrate by crystal growth, a gallium nitride type compound semiconductor layer having a crystal face (0,0,0,1) which can be utilized as the end surface of an optical waveguide or as a cavity mirror surface.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventors: Atsushi Yamaguchi, Akitaka Kimura, Chiaki Sasaoka
  • Patent number: 6096130
    Abstract: A method of crystal growth of a GaN layer with an extremely high surface planarity over a GaAs substrate is provided, wherein a GaAs substrate is heated to a temperature in the range of 600.degree. C. to 700.degree. C. without supplying any group-V element including arsenic to form a Ga-rich surface on the GaAs substrate, before a first source material including N and a second source material including Ga are supplied along with a carrier gas onto a surface of the GaAs substrate to form a GaN layer over the GaAs substrate.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido
  • Patent number: 6033490
    Abstract: In a method of manufacturing a semiconductor device which includes a quartz substrate having a z-cut plane of (0001) plane on a surface, a GaN film is first deposited on the surface. Finally, the quartz substrate is removed from the GaN film. The removed GaN film is used as a real substrate for forming GaN based compound semiconductor layers thereon.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: March 7, 2000
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Chiaki Sasaoka, Koichi Izumi
  • Patent number: 6028877
    Abstract: In accordance with the first present invention, a cladding layer is provided between a gallium nitride based semiconductor active region and a substrate made of a material having a refraction index which is not lager than a refraction index of gallium nitride. The cladding layer includes at least one Al.sub.x Ga.sub.1-x N layer. An averaged value of the index "x" of aluminum of the above at least one Al.sub.x Ga.sub.1-x N layer is in the range of not less than 0.01 to less than 0.05 and a total thickness of the above at least one Al.sub.x Ga.sub.1-x N layer is not less than 0.7 micrometers as well as the cladding layer has an averaged refractive index which is lower than the refractive index of gallium nitride.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: February 22, 2000
    Assignee: NEC Corporation
    Inventor: Akitaka Kimura
  • Patent number: 5963787
    Abstract: A magnesium-doped semiconductor layer expressed by general formula Al.sub.x Ga.sub.1-x N (where 0.ltoreq.x.ltoreq.1) is formed on a substrate. Thereafter, on the semiconductor layer, a plurality of semiconductor layers (including an activation layer) expressed by general formula In.sub.x Al.sub.y Ga.sub.1-x-y N (where 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, 0.ltoreq.x+y.ltoreq.1) are formed. The crystalline characteristics of semiconductor layers including a light emitting layer of a gallium nitride semiconductor light emitting device having a magnesium-doped gallium nitride semiconductor layer are good. Thus, in the case that the light emitting device is a laser device, it can be expected that the oscillating threshold value of the laser device becomes low. In the case that the light emitting device is a light emitting diode, it can be expected that the light emitting efficiency of the light emitting diode becomes high.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: October 5, 1999
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Chiaki Sasaoka
  • Patent number: 5843227
    Abstract: A crystal growth method for growing on a gallium arsenide (GaAs) substrate a gallium nitride (GaN) film which is good in surface flatness and superior in crystallinity. According to the method, a GaAs substrate having a surface which is inclined with respect to the GaAs(100) face is used. The inclination angle of the substrate surface is larger than 0 degree but smaller than 35 degrees with respect to the GaAs(100) face. The inclination direction of the substrate surface is within a range of an angular range from the ?0,0,1! direction of GaAs to the ?0,-1,0! direction past the ?0,-1,1! direction and angles less than 5 degrees on opposite sides of the angular range around an ?1,0,0! direction of gallium arsenide taken as an axis, or within another range crystallographically equivalent to the range. The GaN layer is formed on the surface of the GaAs substrate preferably by hydride vapor deposition method.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: December 1, 1998
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido, Atsushi Yamaguchi
  • Patent number: 5825053
    Abstract: In a heterostructure III-V nitride semiconductor device, an InP substrate has a surface having a sloped angle of 0.degree. to 16.degree. with respect to a (100) surface thereof. At least one GaN layer is formed on the InP substrate.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: October 20, 1998
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido, Atsushi Yamaguchi
  • Patent number: 5559820
    Abstract: A stripe structure including an MQW active layer has a width equal to or smaller than twice the diffusion length of holes, and a p type semiconductor layer for injecting holes into the MQW active layer is formed on both sides of the stripe structure in contact with the sides of the stripe structure. Even when any MQW structure is used as the MQW active layer in order to reduce the temperature dependency of the threshold current, holes are injected into QW layers from the p type semiconductor layer which is in direct contact with all the QW layers in the MQW active layer, so that no local presence of holes in some QW layers occurs. Since the width of the stripe structure is equal to or smaller than twice the diffusion length of holes, the holes are uniformly injected in the direction parallel to the QW surface.
    Type: Grant
    Filed: July 7, 1995
    Date of Patent: September 24, 1996
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Masaaki Nido, Akihisa Tomita, Akira Suzuki
  • Patent number: 5425042
    Abstract: A refractive index control optical semiconductor device includes a semiconductor p-n junction structure, and a refractive index control semiconductor layer. The semiconductor p-n junction structure outputs light with a forward current. The refractive index control semiconductor layer is formed on a semiconductor substrate, is stacked on the semiconductor p-n junction structure to constitute an optical waveguide, causes a refractive index change of light to occur by carrier injection, and includes a multi-quantum well structure formed by alternately stacking a semiconductor quantum well layer and a barrier layer having a bandgap larger than that of the semiconductor quantum well layer at a plurality of periods. The semiconductor quantum well layer has a lattice constant smaller than that of the semiconductor substrate.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: June 13, 1995
    Assignee: NEC Corporation
    Inventors: Masaaki Nido, Akitaka Kimura
  • Patent number: 4356214
    Abstract: A method of forming a puncture preventing layer on an innner surface of a pneumatic tire including the steps of extruding sealing material and pulverizing the extruded sealing material into fine particles for coating the inner surface with a layer of the sealing material under pressure through action of centrifugal force. For effecting the above described method in an efficient manner, there is also provided a puncture preventing layer forming apparatus which includes arrangements for holding the tire, extruding the sealing material, and pulverizing the extruded sealing material so as to be coated onto the inner surface of the tire through the action of centrifugal force.
    Type: Grant
    Filed: December 31, 1980
    Date of Patent: October 26, 1982
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Kozi Soeda, Katuyuki Hoshikawa, Akitaka Kimura
  • Patent number: 4262624
    Abstract: A method of forming a puncture preventing layer on an inner surface of a pneumatic tire including the steps of extruding sealing material and pulverizing the extruded sealing material into fine particles for coating the inner surface with a layer of the sealing material under pressure through action of centrifugal force. For effecting the above described method in an efficient manner, there is also provided a puncture preventing layer forming apparatus which includes arrangements for holding the tire, extruding the sealing material, and pulverizing the extruded sealing material so as to be coated onto the inner surface of the tire through the action of centrifugal force.
    Type: Grant
    Filed: November 9, 1978
    Date of Patent: April 21, 1981
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Kozi Soeda, Katuyuki Hoshikawa, Akitaka Kimura
  • Patent number: 4057090
    Abstract: Pneumatic tire including a puncture sealing layer which is applied to an inner lining and in which by addition of specific amounts of polyisobutylene and of a particular form of silica with respect to a set amount of polybutene and by use of powdered elastomer having a specific particle size distribution there are achieved optimum values of viscosity and adhesivity and ability to seal even large puncture holes in a wide range of temperature and operating conditions. In addition there is less tendency for puncture sealing layer components to migrate to the inner lining and tire durability is therefore improved.
    Type: Grant
    Filed: September 21, 1976
    Date of Patent: November 8, 1977
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Katuyuki Hoshikawa, Soji Noda, Akitaka Kimura