Patents by Inventor Akiyoshi Aoyagi

Akiyoshi Aoyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140008674
    Abstract: A mounting substrate includes: a wiring substrate; and a plurality of optical elements mounted on a mounting surface of the wiring substrate, and each having a first electrode and a second electrode. The wiring substrate includes a support substrate, a plurality of first wires, and a plurality of second wires. The first wires and the second wires are provided within a layer between the support substrate and the mounting surface. The first wires are electrically connected with the first electrodes. The second wires are electrically connected with the second electrodes, and each have cross-sectional area larger than cross-sectional area of each of the first wires.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 9, 2014
    Applicant: SONY CORPORATION
    Inventors: Toshihiko Watanabe, Yoichi Ohshige, Masato Doi, Akiyoshi Aoyagi
  • Patent number: 8537527
    Abstract: A mounting board includes two or more metal layers including the outermost metal layer, and a plurality of metal portions, both of which are formed on a substrate. The plurality of metal portions are formed between a first metal layer of the two or more metal layers and a second metal layer of the two or more metal layers, the first metal layer being the outermost metal layer and the second metal layer being different from the outermost metal layer. The second metal layer includes a plurality of first wiring layers extending in a first direction in a plane. The first metal layer is arranged in zigzags in a second direction intersecting with the first direction and includes a plurality of contact pads connected correspondingly to the plurality of first wiring layers through the metal portions.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Sony Corporation
    Inventors: Akiyoshi Aoyagi, Eizo Okamoto
  • Patent number: 8384116
    Abstract: Disclosed herein is a substrate with chip mounted thereon, including: a solder pattern having a plan-view shape in which projected parts are projected radially from a central part; and a chip fixed in the state of being aligned to the central part of the solder pattern.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: February 26, 2013
    Assignee: Sony Corporation
    Inventors: Hiizu Ohtorii, Akiyoshi Aoyagi, Katsuhiro Tomoda
  • Publication number: 20100214728
    Abstract: A mounting board includes two or more metal layers including the outermost metal layer, and a plurality of metal portions, both of which are formed on a substrate. The plurality of metal portions are formed between a first metal layer of the two or more metal layers and a second metal layer of the two or more metal layers, the first metal layer being the outermost metal layer and the second metal layer being different from the outermost metal layer. The second metal layer includes a plurality of first wiring layers extending in a first direction in a plane. The first metal layer is arranged in zigzags in a second direction intersecting with the first direction and includes a plurality of contact pads connected correspondingly to the plurality of first wiring layers through the metal portions.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 26, 2010
    Inventors: Akiyoshi Aoyagi, Eizo Okamoto
  • Patent number: 7728431
    Abstract: Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underlying metal layer for an external connection electrode, the electronic component including a recess or/and a projection configured to be provided under the barrier metal layer outside or/and inside the opening, the underlying metal layer being formed on the recess or/and the projection and having a surface shape that follows the recess or/and the projection.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: June 1, 2010
    Assignee: Sony Corporation
    Inventors: Yoshimichi Harada, Akiyoshi Aoyagi, Hiroshi Asami
  • Publication number: 20100123163
    Abstract: Disclosed herein is a substrate with chip mounted thereon, including: a solder pattern having a plan-view shape in which projected parts are projected radially from a central part; and a chip fixed in the state of being aligned to the central part of the solder pattern.
    Type: Application
    Filed: November 20, 2009
    Publication date: May 20, 2010
    Applicant: SONY CORPORATION
    Inventors: Hiizu Ohtorii, Akiyoshi Aoyagi, Katsuhiro Tomoda
  • Patent number: 7508080
    Abstract: A method of manufacturing a semiconductor device includes: forming a protective film including an opening on a wiring board having an interconnect pattern so that the protective film has an uneven surface and a part of the interconnect pattern is exposed in the opening; and mounting a semiconductor chip including an electrode on the wiring board so that the part of the interconnect pattern exposed in the opening faces and is electrically connected with the electrode. The protective film is formed so that a recess of the uneven surface does not pierce the protective film.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: March 24, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Patent number: 7344971
    Abstract: A manufacturing method of a semiconductor device comprises: (a) setting up a paste including a resin on an electrical connection part which is electrically connected to a semiconductor substrate; (b) setting up a soldering material above the electrical connection part so as to be in contact with the paste; and (c) forming an external terminal from the soldering material and forming a reinforcement from the paste by fusing the soldering material and the paste. The reinforcement exposes part of the external terminal and covers a periphery of an edge of a base connected to the electrical connection part of the external terminal.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: March 18, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20070290343
    Abstract: Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underlying metal layer for an external connection electrode, the electronic component including a recess or/and a projection configured to be provided under the barrier metal layer outside or/and inside the opening, the underlying metal layer being formed on the recess or/and the projection and having a surface shape that follows the recess or/and the projection.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 20, 2007
    Inventors: Yoshimichi Harada, Akiyoshi Aoyagi, Hiroshi Asami
  • Publication number: 20070252285
    Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.
    Type: Application
    Filed: June 29, 2007
    Publication date: November 1, 2007
    Inventors: Masakuni Shiozawa, Akiyoshi Aoyagi
  • Patent number: 7256072
    Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: August 14, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Masakuni Shiozawa, Akiyoshi Aoyagi
  • Patent number: 7230329
    Abstract: A method is provided to realize a three-dimensional mounting structure of different types of packages. By bonding protruding electrodes onto lands, which are formed on a first carrier substrate, second and third carrier substrates are mounted on the first carrier substrate such that ends of the second and third carrier substrates are arranged above a semiconductor chip.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: June 12, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Toshihiro Sawamoto, Hirohisa Nakayama, Akiyoshi Aoyagi
  • Patent number: 7226808
    Abstract: A method of manufacturing a semiconductor device includes providing resin on at least a partial area on a first semiconductor package and coupling a second semiconductor package to the first semiconductor package electrically while the resin maintains its fluidity.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: June 5, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Patent number: 7190063
    Abstract: A semiconductor device is provided that comprises: a first semiconductor package including a first substrate having a first pad; a second semiconductor package including a second substrate having a second pad which is mounted on the first semiconductor package; and solder provided between the first and second substrates that electrically couples each of the first pads and each of the second pads. Only the solder at the corner portions of the first substrate is covered with resin.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: March 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Patent number: 7176561
    Abstract: A semiconductor device includes a first package, a second package, a contact part for electrically coupling a first wiring pattern to a second wiring pattern, and a reinforcer. The thermal expansion coefficient of the first package is larger than that of the second package. The second package is disposed so that the second interposer overlaps the first semiconductor chip and the first interposer. The contact part is provided between the first and second interposers so that a first end is coupled to the first wiring pattern and a second end is coupled to the second wiring pattern. The reinforcer is provided to expose part of the contact part and cover the circumference of the first end of the contact part.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: February 13, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Patent number: 7141873
    Abstract: A semiconductor device including: a semiconductor chip; a wiring board on which the semiconductor chip is mounted; and a plurality of external terminals provided on the wiring board. The external terminals include at least one first external terminal and two or more second external terminals. The first external terminal is formed of a soldering material. Each of the second external terminals includes a soldering material and a plurality of particles formed of a resin and dispersed in the soldering material. The second external terminals are a pair of external terminals among the external terminals, and a distance between the pair of external terminals is greater than a distance between any other pair of external terminals among the external terminals.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: November 28, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Patent number: 7091619
    Abstract: A method is provided to enhance the connection reliability in three-dimensional mounting while considering the warping of packages. Opening diameters of the openings provided corresponding to protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of a carrier substrate, and the opening diameters of openings provided corresponding to the protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of another carrier substrate.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: August 15, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20060125096
    Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.
    Type: Application
    Filed: February 2, 2006
    Publication date: June 15, 2006
    Inventors: Masakuni Shiozawa, Akiyoshi Aoyagi
  • Patent number: 7045394
    Abstract: A method of manufacturing a semiconductor device is provided. A semiconductor module is prepared which has a wiring board and a plurality of semiconductor chips mounted on a first face of the wiring board. The semiconductor chips overlap a central region of the wiring board and an edge region of the wiring board surround the central region. An adhesive tape is located opposite the first face of the wiring board, followed by sticking the adhesive tape to the semiconductor module by a roller. Thereafter, the resulting semiconductor module is cut from a second face side of the wiring board to yield the device. The roller has a central portion and two end portions. The central portion presses the adhesive tape from above the central region. The end portions press the adhesive tape from above the two end regions.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: May 16, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Shiro Sato, Akiyoshi Aoyagi
  • Publication number: 20050263868
    Abstract: A semiconductor device includes a first package, a second package, a contact part for electrically coupling a first wiring pattern to a second wiring pattern, and a reinforcer. The thermal expansion coefficient of the first package is larger than that of the second package. The second package is disposed so that the second interposer overlaps the first semiconductor chip and the first interposer. The contact part is provided between the first and second interposers so that a first end is coupled to the first wiring pattern and a second end is coupled to the second wiring pattern. The reinforcer is provided to expose part of the contact part and cover the circumference of the first end of the contact part.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 1, 2005
    Inventor: Akiyoshi Aoyagi