Patents by Inventor Akiyoshi Aoyagi

Akiyoshi Aoyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050266614
    Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor chip on each partitioned region of a frame substrate partitioned for each first semiconductor package; mounting a second semiconductor package, where a second semiconductor chip is mounted, on each partitioned region of the frame substrate so as to be arranged above the first semiconductor chip; and cutting the frame substrate, where the second semiconductor package is mounted, for each partitioned region of the frame substrate.
    Type: Application
    Filed: April 28, 2004
    Publication date: December 1, 2005
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050266701
    Abstract: A semiconductor chip includes a first package, a second package, a contact part for electrically coupling a first wiring pattern and a second wiring pattern, a reinforcing part, and an adhesive part. The first package has a larger coefficient of thermal expansion than the second package. The second package is placed so that a second interposer overlaps a first semiconductor chip and a first interposer. The contact part has a first end coupled to the first wiring pattern and a second end coupled to the second wiring pattern. The contact part is provided between the first interposer the second interposer. The reinforcing part exposes part of the contact part and covers the periphery of the first end of the contact part. The adhesive part is provided between the first interposer and the second interposer so as not to come in contact with the contact part, and joins the first package and the second package.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 1, 2005
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050266671
    Abstract: A manufacturing method of a semiconductor device comprises: (a) setting up a paste including a resin on an electrical connection part which is electrically connected to a semiconductor substrate; (b) setting up a soldering material above the electrical connection part so as to be in contact with the paste; and (c) forming an external terminal from the soldering material and forming a reinforcement from the paste by fusing the soldering material and the paste. The reinforcement exposes part of the external terminal and covers a periphery of an edge of a base connected to the electrical connection part of the external terminal.
    Type: Application
    Filed: May 24, 2005
    Publication date: December 1, 2005
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050184379
    Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.
    Type: Application
    Filed: March 29, 2005
    Publication date: August 25, 2005
    Inventors: Masakuni Shiozawa, Akiyoshi Aoyagi
  • Patent number: 6911721
    Abstract: A semiconductor device includes a base substrate provided with a base wiring. A first substrate includes a first wiring to be electrically connected to the base wiring and is provided above the base substrate. A first semiconductor element includes a first electrode to be electrically connected to the first wiring and is provided between the base substrate and the first substrate. A second substrate includes a second wiring to be electrically connected to the base wiring and is provided above the first substrate. A second semiconductor element includes a second electrode to be electrically connected to the second wiring and is provided between the first substrate and the second substrate and above the first semiconductor element. The first substrate has a first region where the first semiconductor element is provided below, a second region where a portion of the first wiring that connects to the base wiring is located, and a first bent section between the first region and the second region.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: June 28, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050118791
    Abstract: A method of manufacturing a semiconductor device is provided. A semiconductor module is prepared which has a wiring board and a plurality of semiconductor chips mounted on a first face of the wiring board. The semiconductor chips overlap a central region of the wiring board and an edge region of the wiring board surround the central region. An adhesive tape is located opposite the first face of the wiring board, followed by sticking the adhesive tape to the semiconductor module by a roller. Thereafter, the resulting semiconductor module is cut from a second face side of the wiring board to yield the device. The roller has a central portion and two end portions. The central portion presses the adhesive tape from above the central region. The end portions press the adhesive tape from above the two end regions.
    Type: Application
    Filed: October 26, 2004
    Publication date: June 2, 2005
    Inventors: Shiro Sato, Akiyoshi Aoyagi
  • Publication number: 20050110166
    Abstract: A method and device are provided to realize a structure in which different kinds of chips are three-dimensionally mounted while allowing for proper heat dissipation. A semiconductor package PK12 in which stacked semiconductor chips 33a and 33b are wire-connected is stacked on a semiconductor package PK11 in which a semiconductor chip 23 is mounted by anisotropic conductive film (ACF) bonding. A carrier substrate 31 is mounted on a carrier substrate 21 in a state where the reverse face of the semiconductor chip 23 is exposed.
    Type: Application
    Filed: March 16, 2004
    Publication date: May 26, 2005
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050110158
    Abstract: A semiconductor device is provided that comprises: a first semiconductor package including a first substrate having a first pad; a second semiconductor package including a second substrate having a second pad which is mounted on the first semiconductor package; and solder provided between the first and second substrates that electrically couples each of the first pads and each of the second pads. Only the solder at the corner portions of the first substrate is covered with resin.
    Type: Application
    Filed: October 8, 2004
    Publication date: May 26, 2005
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050104213
    Abstract: An electric connection terminal includes a brazing material, a plurality of particles dispersed in the brazing material and made of a resin, and a conductor film that coats a surface of each of the particles.
    Type: Application
    Filed: October 5, 2004
    Publication date: May 19, 2005
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050098885
    Abstract: A semiconductor device including: a semiconductor chip; a wiring board on which the semiconductor chip is mounted; and a plurality of external terminals provided on the wiring board. The external terminals include at least one first external terminal and two or more second external terminals. The first external terminal is formed of a soldering material. Each of the second external terminals includes a soldering material and a plurality of particles formed of a resin and dispersed in the soldering material. The second external terminals are a pair of external terminals among the external terminals, and a distance between the pair of external terminals is greater than a distance between any other pair of external terminals among the external terminals.
    Type: Application
    Filed: October 4, 2004
    Publication date: May 12, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050095746
    Abstract: A method of manufacturing a semiconductor device includes: forming a protective film including an opening on a wiring board having an interconnect pattern so that the protective film has an uneven surface and a part of the interconnect pattern is exposed in the opening; and mounting a semiconductor chip including an electrode on the wiring board so that the part of the interconnect pattern exposed in the opening faces and is electrically connected with the electrode. The protective film is formed so that a recess of the uneven surface does not pierce the protective film.
    Type: Application
    Filed: September 16, 2004
    Publication date: May 5, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20050001301
    Abstract: A semiconductor device includes a first semiconductor package where a first semiconductor chip is mounted, a second semiconductor package supported above the first semiconductor package so as to be disposed above the first semiconductor chip and resin disposed exposing at least a part of the first semiconductor chip, and provided between the first semiconductor chip and the second semiconductor package.
    Type: Application
    Filed: April 28, 2004
    Publication date: January 6, 2005
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20040238948
    Abstract: A method is provided to suppress detachment between semiconductor packages while preventing dislocation at the time of mounting a stacked semiconductor package on a motherboard. Semiconductor packages PK1 and PK2 are bonded to each other through protruding electrodes and resin is provided between the semiconductor packages PK1 and PK2. The resin is provided in the peripheries of the protruding electrodes so as to contact each of the protruding electrodes while not contacting a semiconductor chip.
    Type: Application
    Filed: March 23, 2004
    Publication date: December 2, 2004
    Inventors: Masakuni Shiozawa, Akiyoshi Aoyagi
  • Publication number: 20040222519
    Abstract: A method and device are provided to realize a structure in which different kinds of chips are three-dimensionally mounted while suppressing the deterioration of the connection reliability. A semiconductor package PK12 in which a semiconductor chip 13 is sealed with a sealing resin 17 is stacked on a semicoductor package PK11 in which a semiconductor chip 3 is mounted on a carrier substrate 1 by anisotropic conductive film (ACF) bonding. The range in which the semiconductor chip 13 is sealed with a sealing resin 17 is set so as to cover the semiconductor chip 13 and to be attached to the region for arranging the protruding electrodes 16 on the side of the surface on which the semiconductor chip 13 is mounted.
    Type: Application
    Filed: March 16, 2004
    Publication date: November 11, 2004
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20040222534
    Abstract: A method is provided to realize a three-dimensional mounting structure of different types of packages. By bonding protruding electrodes onto lands, which are formed on a first carrier substrate, second and third carrier substrates are mounted on the first carrier substrate such that ends of the second and third carrier substrates are arranged above a semiconductor chip.
    Type: Application
    Filed: February 6, 2004
    Publication date: November 11, 2004
    Inventors: Toshihiro Sawamoto, Hirohisa Nakayama, Akiyoshi Aoyagi
  • Publication number: 20040222508
    Abstract: A method and device are provided to realize a structure in which different kinds of chips are three-dimensionally mounted while suppressing the warpage of a carrier substrate. A semiconductor package PK12 in which stacked semiconductor chips 33a and 33b are wire-bonded to the carrier substrate 31 is stacked on a semiconductor package PK11 in which semiconductor chips 23a and 23b are mounted on both faces of the carrier substrate 21 by ACF bonding.
    Type: Application
    Filed: March 16, 2004
    Publication date: November 11, 2004
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20040222510
    Abstract: A method is provided to enhance the connection reliability in three-dimensional mounting while considering the warping of packages. Opening diameters of the openings provided corresponding to protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of a carrier substrate, and the opening diameters of openings provided corresponding to the protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of another carrier substrate.
    Type: Application
    Filed: March 19, 2004
    Publication date: November 11, 2004
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20040217380
    Abstract: A device and method are provided for preventing a protruding electrode from being melted during mounting of a carrier substrate. A first protruding electrode whose melting point is lower than that of a second protruding electrode is provided on a land that is formed on the back surface of a carrier substrate. The first protruding electrode is bonded on a land on a mother substrate by reflow processing at a temperature that is lower than the melting point of the second protruding electrode and higher than the melting point of the first protruding electrode.
    Type: Application
    Filed: February 25, 2004
    Publication date: November 4, 2004
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20040135243
    Abstract: A semiconductor device includes a base substrate including a base wiring pattern. A first circuit substrate is disposed over the base substrate and includes a first wiring pattern. A first semiconductor element is mounted on the first circuit substrate and includes a first electrode that is electrically connected to the first wiring pattern. A second circuit substrate is disposed over the first circuit substrate and includes a second wiring pattern and a second semiconductor element is mounted on the second circuit substrate and includes a second electrode that is electrically connected to the second wiring pattern. A first protruded electrode is electrically connected to the first wiring pattern and provided protruding from the first circuit substrate and bonded to the base wiring pattern and a second protruded electrode is electrically connected to the second wiring pattern and provided protruding from the second circuit substrate and bonded to the base wiring pattern.
    Type: Application
    Filed: November 21, 2003
    Publication date: July 15, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akiyoshi Aoyagi
  • Publication number: 20040094831
    Abstract: A semiconductor device includes a base substrate provided with a base wiring. A first substrate includes a first wiring to be electrically connected to the base wiring and is provided above the base substrate. A first semiconductor element includes a first electrode to be electrically connected to the first wiring and is provided between the base substrate and the first substrate. A second substrate includes a second wiring to be electrically connected to the base wiring and is provided above the first substrate. A second semiconductor element includes a second electrode to be electrically connected to the second wiring and is provided between the first substrate and the second substrate and above the first semiconductor element. The first substrate has a first region where the first semiconductor element is provided below, a second region where a portion of the first wiring that connects to the base wiring is located, and a first bent section between the first region and the second region.
    Type: Application
    Filed: August 21, 2003
    Publication date: May 20, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Akiyoshi Aoyagi