Patents by Inventor Akram A. Salman
Akram A. Salman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006407Abstract: The present disclosure generally relates to an electrostatic discharge (ESD) protection circuit in an integrated circuit and methods of forming such. In an example, an integrated circuit includes a transistor, a doped buried layer, and a capacitor. The transistor includes source and drain regions and a gate structure. The source and drain regions have a first conductivity type and are disposed in a semiconductor layer. The semiconductor layer has an opposite second conductivity type. The doped buried layer has the first conductivity type disposed in the semiconductor layer below the source and drain regions. The capacitor is disposed in the semiconductor layer and includes first and second capacitor electrodes extending to the doped buried layer. The first capacitor electrode electrically couples the drain region. The second capacitor electrode electrically couples the gate structure and conductively contacts the doped buried layer. The doped buried layer electrically couples the source region.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Kuo Yao Lin, Akram Salman
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Patent number: 11658176Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.Type: GrantFiled: September 28, 2020Date of Patent: May 23, 2023Assignee: Texas Instruments IncorporatedInventors: Zaichen Chen, Akram A. Salman, Binghua Hu
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Publication number: 20230138308Abstract: An integrated circuit (IC), comprising a fuse structure (eFuse) formed in a resistive layer over a semiconductor substrate, the eFuse subject to a change in resistance through the controlled application of a programming current from a programming voltage source connected to a first terminal of the eFuse; a blow transistor formed on or over the substrate and having a control terminal configured to cause the programming current to flow through the eFuse in response to a programming signal; an intermediate transistor formed on or over the substrate and electrically coupled in series between a second terminal of the eFuse and the blow transistor; and, control circuitry formed on or over the substrate and electrically coupled to a node between the second terminal of the eFuse and the intermediate transistor, the control circuitry configured to reduce the flow of programming current through the eFuse in the event that a voltage detected at the node reaches a threshold level.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Anand Seshadri, Kemal Tamer San, Sunil Kumar Dusa, Michael Ball, Akram A. Salman
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Patent number: 11574903Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.Type: GrantFiled: August 1, 2017Date of Patent: February 7, 2023Assignee: Texas Instmments IncorporatedInventors: Henry Litzmann Edwards, Akram A. Salman, Md Iqbal Mahmud
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Publication number: 20220392886Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Inventors: Henry Litzmann EDWARDS, Akram A. SALMAN, Binghua Hu
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Patent number: 11444075Abstract: An integrated circuit (IC) includes a semiconductor substrate in which a plurality of spaced-apart deep trench (DT) structures are formed. The IC further includes a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures. Each of the DEEPN diffusion regions merges with at least one neighboring DEEPN diffusion region that surrounds at least one neighboring DT structure. The merged DEEPN diffusion regions may partially isolate two electronic devices, e.g. ESD devices.Type: GrantFiled: October 29, 2019Date of Patent: September 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Akram A. Salman, Binghua Hu
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Publication number: 20220189946Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: ApplicationFiled: March 4, 2022Publication date: June 16, 2022Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
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Patent number: 11302688Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: GrantFiled: August 3, 2018Date of Patent: April 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
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Patent number: 11049852Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.Type: GrantFiled: August 3, 2018Date of Patent: June 29, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
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Patent number: 10930641Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.Type: GrantFiled: December 5, 2018Date of Patent: February 23, 2021Assignee: Texas Instruments IncorporatedInventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
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Publication number: 20210013193Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.Type: ApplicationFiled: September 28, 2020Publication date: January 14, 2021Inventors: ZAICHEN CHEN, AKRAM A. SALMAN, BINGHUA HU
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Patent number: 10790275Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.Type: GrantFiled: November 21, 2018Date of Patent: September 29, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Zaichen Chen, Akram A. Salman, Binghua Hu
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Publication number: 20200161292Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.Type: ApplicationFiled: November 21, 2018Publication date: May 21, 2020Inventors: ZAICHEN CHEN, AKRAM A. SALMAN, BINGHUA HU
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Patent number: 10607984Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.Type: GrantFiled: June 18, 2019Date of Patent: March 31, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yang Xiu, Aravind C. Appaswamy, Akram Salman, Mariano Dissegna
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Publication number: 20200066710Abstract: An integrated circuit (IC) includes a semiconductor substrate in which a plurality of spaced-apart deep trench (DT) structures are formed. The IC further includes a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures. Each of the DEEPN diffusion regions merges with at least one neighboring DEEPN diffusion region that surrounds at least one neighboring DT structure. The merged DEEPN diffusion regions may partially isolate two electronic devices, e.g. ESD devices.Type: ApplicationFiled: October 29, 2019Publication date: February 27, 2020Inventors: Henry Litzmann EDWARDS, Akram A. SALMAN, Binghua HU
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Patent number: 10461072Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.Type: GrantFiled: February 13, 2018Date of Patent: October 29, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Akram A. Salman, Binghua Hu
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Publication number: 20190304964Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Inventors: Yang Xiu, Arvind C. Appaswamy, Akram Salman, Mariano Dissegna
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Patent number: 10396199Abstract: A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.Type: GrantFiled: June 16, 2017Date of Patent: August 27, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Aravind C. Appaswamy, Akram A. Salman, Farzan Farbiz, Gianluca Boselli
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Patent number: 10381342Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.Type: GrantFiled: June 3, 2016Date of Patent: August 13, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yang Xiu, Aravind C Appaswamy, Akram Salman, Mariano Dissegna
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Patent number: 10373944Abstract: Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.Type: GrantFiled: February 28, 2017Date of Patent: August 6, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Akram A. Salman, Muhammad Yusuf Ali