Patents by Inventor Akshey Sehgal
Akshey Sehgal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10818557Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.Type: GrantFiled: July 3, 2018Date of Patent: October 27, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
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Patent number: 10714380Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.Type: GrantFiled: October 26, 2018Date of Patent: July 14, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Ravi P. Srivastava, Sipeng Gu, Sunil K. Singh, Xinyuan Dou, Akshey Sehgal, Zhiguo Sun
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Publication number: 20200135545Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Inventors: Ravi P. SRIVASTAVA, Sipeng GU, Sunil K. SINGH, Xinyuan DOU, Akshey SEHGAL, Zhiguo SUN
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Publication number: 20200013678Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.Type: ApplicationFiled: July 3, 2018Publication date: January 9, 2020Inventors: Sipeng Gu, Akshey Sehgal, Xinyuan Dou, Sunil K. Singh, Ravi P. Srivastava, Haiting Wang, Scott H. Beasor
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Patent number: 10347528Abstract: Methods of forming an interconnect of an IC are disclosed. The methods etch a wire trench opening partially into an ILD layer using a hard mask, and form a metal liner sidewall spacer on sidewalls of the wire trench opening, prior to etching via openings that create a via-wire opening with the wire trench opening. The metal liner sidewall spacer protects against chamfering during the via etch and/or removal of an etch stop layer over conductive structures in an underlying ILD layer. In one embodiment, a barrier liner is deposited over the metal liner sidewall spacer, creating a double layered sidewall spacer on the sidewalls of the wire trench opening portion of the via-wire opening. A conductor is deposited to form a unitary via-wire conductive structure. An interconnect includes the double layered sidewall spacer on the sidewalls of a wire trench opening portion of the via-wire conductive structure.Type: GrantFiled: March 6, 2018Date of Patent: July 9, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Sunil K. Singh, Ravi P. Srivastava, Sipeng Gu, Akshey Sehgal
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Patent number: 10181420Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.Type: GrantFiled: February 6, 2017Date of Patent: January 15, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Jason Eugene Stephens, David Michael Permana, Guillaume Bouche, Andy Wei, Mark Zaleski, Anbu Selvam K M Mahalingam, Craig Michael Child, Jr., Roderick Alan Augur, Shyam Pal, Linus Jang, Xiang Hu, Akshey Sehgal
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Patent number: 10134876Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.Type: GrantFiled: March 31, 2017Date of Patent: November 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Bharat V. Krishnan, Timothy J. McArdle, Rinus Tek Po Lee, Shishir K. Ray, Akshey Sehgal
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Patent number: 10121711Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.Type: GrantFiled: August 3, 2015Date of Patent: November 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
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Publication number: 20180286982Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs with strained channels and reduced on state resistances and methods of manufacture. The structure includes: a plurality of fin structures comprising doped source and drain regions with a diffusion blocking layer between the doped source and drain regions and an underlying fin region formed within dielectric material.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Bharat V. KRISHNAN, Timothy J. MCARDLE, Rinus Tek Po LEE, Shishir K. Ray, Akshey SEHGAL
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Publication number: 20180226294Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.Type: ApplicationFiled: February 6, 2017Publication date: August 9, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Jason Eugene STEPHENS, David Michael PERMANA, Guillaume BOUCHE, Andy WEI, Mark ZALESKI, Anbu Selvam KM MAHALINGAM, Craig Michael CHILD, JR., Roderick Alan AUGUR, Shyam PAL, Linus JANG, Xiang HU, Akshey SEHGAL
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Patent number: 9576894Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.Type: GrantFiled: June 3, 2015Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang
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Publication number: 20170025347Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.Type: ApplicationFiled: February 12, 2016Publication date: January 26, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
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Publication number: 20160358851Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.Type: ApplicationFiled: June 3, 2015Publication date: December 8, 2016Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang
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Patent number: 9293363Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.Type: GrantFiled: July 21, 2015Date of Patent: March 22, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
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Patent number: 9281249Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.Type: GrantFiled: January 15, 2014Date of Patent: March 8, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Alok Vaid, Abner Bello, Sipeng Gu, Lokesh Subramany, Xiang Hu, Akshey Sehgal
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Publication number: 20150348913Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.Type: ApplicationFiled: August 4, 2015Publication date: December 3, 2015Applicant: Globalfoundries Inc.Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
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Publication number: 20150340296Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.Type: ApplicationFiled: August 3, 2015Publication date: November 26, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
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Publication number: 20150332959Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.Type: ApplicationFiled: July 21, 2015Publication date: November 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
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Publication number: 20150287595Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.Type: ApplicationFiled: May 29, 2015Publication date: October 8, 2015Inventors: Andy WEI, Mariappan HARIHARAPUTHIRAN, Dae Geun YANG, Dae-Han CHOI, Xiang HU, Richard J. CARTER, Akshey SEHGAL
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Publication number: 20150270175Abstract: Provided herein are approaches for forming a fin field-effect-transistor (FinFET) device using a partially crystallized fin hard mask. Specifically, a hard mask is patterned over a substrate, and the FinFET device is annealed to form a set of crystallized hard mask elements adjacent a set of non-crystallized hard mask elements. A masking structure is provided over a first section of the patterned hard mask to prevent the set of non-crystallized hard mask elements from being crystallized during the anneal. During a subsequent fin cut process, the non-crystallized mask elements are removed, while crystallized mask elements remain. A set of fins is then formed in the FinFET device according to the location(s) of the crystallized mask elements.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Xiang Hu, Andy Chih-Hung Wei, Dae-han Choi, Mariappan Hariharaputhiran, Weihua Tong, Dae Geun Yang, Akshey Sehgal, Jing Wan