Patents by Inventor Akshey Sehgal

Akshey Sehgal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150255353
    Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing WAN, Andy WEI, Jinping LIU, Xiang HU, Dae-han CHOI, Dae Geun YANG, Churamani GAIRE, Akshey SEHGAL
  • Patent number: 9129905
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 8, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Patent number: 9121890
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Patent number: 9117822
    Abstract: Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: August 25, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sunil K. Singh, Ravi P. Srivastava, Mark A. Zaleski, Akshey Sehgal
  • Patent number: 9105478
    Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: August 11, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy Wei, Mariappan Hariharaputhiran, Dae Geun Yang, Dae-Han Choi, Xiang Hu, Richard J. Carter, Akshey Sehgal
  • Patent number: 9105507
    Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: August 11, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
  • Publication number: 20150198435
    Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Alok VAID, Abner BELLO, Sipeng GU, Lokesh SUBRAMANY, Xiang HU, Akshey SEHGAL
  • Publication number: 20150123214
    Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.
    Type: Application
    Filed: January 13, 2015
    Publication date: May 7, 2015
    Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
  • Publication number: 20150123212
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Publication number: 20150115418
    Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Andy WEI, Mariappan HARIHARAPUTHIRAN, Dae Geun YANG, Dae-Han CHOI, Xiang HU, Richard J. CARTER, Akshey SEHGAL
  • Publication number: 20150115267
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Patent number: 8969932
    Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
  • Patent number: 8835233
    Abstract: A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 16, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Andy C. Wei, Akshey Sehgal, Bamidele S. Allimi
  • Publication number: 20140159126
    Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
  • Publication number: 20140004692
    Abstract: A method for fabricating a multiple-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches. Still further, the method includes depositing a third workfunction material in a layer in the plurality of trenches.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andy C. Wei, Akshey Sehgal, Bamidele S. Allimi
  • Publication number: 20120067396
    Abstract: A solar concentrator is implemented with a plate structure that has a surface and one or more hydrophobic regions on the surface of the plate structure. The plate structure is transparent to visible light. A fluid is sprayed onto the surface of the plate structure where the fluid forms droplets on the hydrophobic regions. The droplets capture substantially all angles of incident solar radiation and deliver concentrated solar radiation to a corresponding number of solar cells.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Inventors: Visvamohan Yegnashankaran, Akshey Sehgal, Jamal Ramdani
  • Publication number: 20120034756
    Abstract: A number of deep trench openings are formed in a semiconductor wafer to have substantially equal depths and no oxide undercut by forming a number of shallow trench openings, forming a mask structure in the shallow trench openings where the mask structure has a substantially planar top surface, forming a number of mask openings in the mask structure, and etching the semiconductor wafer through the mask openings to form the deep trench openings.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 9, 2012
    Inventors: Taehun Kwon, Akshey Sehgal, Donald Robertson Getchell, Patrick McCarthy, Rodney L. Hill, Yaojian Leng
  • Publication number: 20040050406
    Abstract: A method of enhancing removal of photoresist and/or resist residue from a substrate includes exposing the substrate to an environmentally friendly, non-hazardous co-solvent mixture comprising a carbonate, an oxidizer and an accelerator. The stripping process may be performed under ambient conditions, or in the presence of a supercritical fluid such as supercritical carbon dioxide with the supercritical cleaning step itself being a desirable “green” process. In one embodiment, the co-solvent mixture includes propylene carbonate, benzyl alcohol, hydrogen peroxide and an accelerator such as formic acid. If desired, supercritical carbon dioxide in combination with a second co-solvent mixture may be subsequently applied to the substrate to rinse and dry the substrate. In one embodiment, the second co-solvent mixture includes a lower alkyl alcohol such as isopropyl alcohol.
    Type: Application
    Filed: July 16, 2003
    Publication date: March 18, 2004
    Inventor: Akshey Sehgal