Abstract: Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.

Abstract: Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.

Abstract: A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data.

Abstract: A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.

Abstract: Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.

Abstract: A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data.

Abstract: A method, device, and system are disclosed. In one embodiment the method includes scheduling a thread to run on first core of a multi-core processor. The determination as to which core the thread is scheduled on uses one or more processes. These processes may include ranking all of the cores specific to a workload of the thread, establishing a current utilization of each core of the multi-core processor, and calculating an inter-core migration cost for the thread.

Abstract: A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.

Abstract: A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.

Abstract: A method and apparatus for handling low power and high performance loads is herein described. Software, such as a compiler, is utilized to identify producer loads, consumer reuse loads, and consumer forwarded loads. Based on the identification by software, hardware is able to direct performance of the load directly to a load value buffer, a store buffer, or a data cache. As a result, accesses to cache are reduced, through direct loading from load and store buffers, without sacrificing load performance.

Abstract: A method, device, and system are disclosed. In one embodiment the method includes scheduling a thread to run on first core of a multi-core processor. The determination as to which core the thread is scheduled on uses one or more processes. These processes may include ranking all of the cores specific to a workload of the thread, establishing a current utilization of each core of the multi-core processor, and calculating an inter-core migration cost for the thread.

Abstract: A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.

Abstract: Methods and apparatus to reduce minimum operating voltage through a hybrid cache design are described. In one embodiment, a cache with different size bit cells may be used, e.g., to reduce minimum operating voltage of an integrated circuit device that includes the cache and possibly other logic (such as a processor). Other embodiments are also described.

Abstract: Data in a cache is selectively compressed based on predictions as to whether the benefit of compression in reducing cache misses exceeds the cost of decompressing the compressed data. The prediction is based on an assessment of actual costs and benefits for previous instruction cycles of the same program providing dynamic and concurrent adjustment of compression to maximize the benefits of compression in a variety of applications.