METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE

Abstract

A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.

Description

FIELD

The present invention relates generally to memory, and more particularly to reducing the power consumption of cache memory while a system is in a low power state.

BACKGROUND

Technology advancements have enabled the integration of large on-die embedded Dynamic Random Access Memory (eDRAM) caches with a Central Processing Unit (CPU). Embedded DRAM is significantly denser than traditional Static Random Access Memories (SRAMs), but must be periodically refreshed to retain data. Like SRAM, embedded DRAM is susceptible to device variations, which play a role in determining a refresh period for embedded DRAM cells. Power consumed to refresh eDRAM represents a large portion of overall system power, particularly during low-power states when the CPU is idle.

BRIEF DESCRIPTION OF THE DRAWINGS

Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals depict like parts, and in which:

FIG. 1 is an embodiment of a processor that includes a cache memory and error code correction logic (ECC) according to the principles of the present invention;

FIG. 2 is a block diagram of a system including an embodiment of a Recently Accessed Lines Table (RALT) and the cache memory and ECC logic shown in FIG. 1 illustrating a fast access to a cache line in the cache memory;

FIG. 3 is a block diagram of the system shown in FIG. 2 illustrating a subsequent read of a cache line within the refresh period;

FIG. 4A is a block diagram illustrating an embodiment of an ECC encoder included in the quick ECC logic shown in FIG. 1;

FIG. 4B is a block diagram illustrating an embodiment of an ECC decoder (decoding logic) included in the quick ECC logic shown in FIG. 1;

FIG. 5 is a flow graph illustrating an embodiment of a method for using the system shown in FIG. 1 according to the principles of the present invention; and

FIG. 6 is a block diagram of a system that includes an embodiment of the processor shown in FIG. 1.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.

DETAILED DESCRIPTION

Error-correcting codes (ECC) have are typically used to allow non-volatile memory and storage devices to tolerate both soft and hard errors. On-chip caches in a device and memory devices (chips, integrated circuits) typically use simple and fast ECC such as, Single Error Correction and Double Error Detection (SECDED) Hamming codes. Slower devices such as flash memories use multi-bit ECCs with strong error correcting capabilities, for example, Reed-Solomon codes. The higher decoding latencies of the strong ECC mechanisms do not pose a problem for mass storage devices, for example, disk drives because the encoding/decoding latency is insignificant as compared to intrinsic device access time. However, as a result of technology scaling, the on-chip memory arrays (caches) are more susceptible to multi-bit errors. Thus, strong ECC codes are also desirable for on-chip cache. In addition to the latency overhead, the storage overhead of the additional ECC bits is an obstacle to using multi-bit ECC for on-chip cache memories.

In pursuit of improved power and energy efficiency, micro-processors implement a number of idle states to support lower power modes (states). Reducing the power consumed during idle states is particularly important because the typical Central Processing Unit (CPU) spends a lot of time in idle state. Embedded DRAM technology enables smaller memory cells as compared to SRAM cells, resulting in a large increase in memory density. Thus, DRAM may be used to replace SRAM as the last-level on-chip cache in high performance processors.

However, a problem with embedded DRAM (eDRAM) cells is that the cells lose charge over time due to leakage currents. The retention time of an eDRAM cell is defined as the length of time for which the cell can retain its state (charge). Cell retention time is dependent on the leakage current, which, in turn, is dependent on the device leakage. To preserve the state of stored data, eDRAM cells need to be refreshed on a periodic basis. In order to prevent loss of state in the cache, the refresh period needs to be less than the cell retention time. Since eDRAM is DRAM integrated on a conventional logic process it uses fast logic transistors with a higher leakage current than transistors used in conventional DRAM. Therefore, the refresh time for eDRAM is about a thousand times shorter than conventional DRAM. The shorter refresh period increases power consumed during the idle state and also leads to reduced availability.

In SRAM caches, intrinsic variations force operation at high voltages due to a few weak cells that fail (lose charge (state)) at lower voltages, and impede efforts to reduce power consumption during idle states. Likewise, in embedded DRAM caches, device variations affect the retention time between refresh of individual DRAM cells, with a few particularly weak cells (bits) determining the refresh period of the entire cache. Variations in threshold voltage cause retention times of different DRAM cells to vary significantly. These variations are caused predominantly by random dopant fluctuations and manifest themselves as a random distribution of retention times amongst eDRAM cells. However, increasing the refresh rate significantly increases cache power.

A method to reduce cache power is to use power gates. Power gates are switches on the power supply that allow power to be completely shut off to a block of transistors. Since memory technologies such as eDRAM and SRAM are unable to retain state when deprived of power, power-gating is performed at the cost of losing memory state.

As cache density increases, the performance and power consumption of power gating also increase. As the size of the embedded DRAM cache increases there is a tradeoff between idle exit latency (time to restore the state of the cache by retrieving cache lines from main memory) and power consumption during the idle state.

The DRAM refresh period may be increased through the use of error-correcting codes (ECC) to dynamically identify and repair cells that lose their state. The refresh rate is set irrespective of the weakest eDRAM cells, using ECC to compensate for lost state. A stronger error-correcting code, with the ability to correct multi-bit errors, implies increased refresh rate and reduced power consumption. However, multi-bit ECC codes have a high storage and complexity overhead which limit their applicability.

An embodiment of the present invention provides a flexible memory structure that uses multi-bit ECC codes with a low storage and complexity overhead and can operate at very low idle power, without dramatically increasing transition latency to and from the idle power state due to loss of state of cells (bits).

FIG. 1 is an embodiment of a processor 100 that includes a cache memory and error code correction (ECC) logic 122 according to the principles of the present invention. The ECC logic 122 is low-latency, low-cost, multi-bit error-correcting logic that compensates for high failure rates in volatile memory such as the memory cache 110 shown in FIG. 1. In the embodiment shown, the memory cache 110 is embedded DRAM (eDRAM). In other embodiments, the memory cache 110 may be Static Random Access Memory (SRAM) or any other type of volatile memory

Correcting more errors requires higher redundancy, which leads to a high check bit overhead. For example, to correct t-bit errors in k-bit input data, a BCH code typically requires r=t*ceil(log₂k)+1 check bits. Due to the logarithmic relationship between r and k, the number of check bits increases much slower than the size of the input data. Thus, the ECC check bit overhead is reduced by increasing k.

For example, a Single Error Correcting, Double Error Detecting (SECDED) code for a 64 Byte (512-bit) cache line requires 11 bits which is an overhead of about 2%. The number of bits in an ECC code relative to the number of bits in the data word diminishes as the number of bits in the data word increases. For example, a SECDED code for a 64 Byte cache line has an 11-bit overhead (2%), and a SECDED code for a 1024 Byte (1 KB) cache line has a 15-bit overhead (0.18%).

However, when a large cache line is used, writes to sub-blocks within the cache-line may require the entire cache line to be read every time in order to regenerate the ECC bits. As a linear code, BCH inherits the additive property of linear systems, which ensures that ECC check bits can be updated using only the information of the modified sub-block (chunk of data). The data word d (representing a cache line) is divided into multiple chunks (sub-blocks)[d_i-1,d_i-2, . . . , d₀]. The G matrix used in ECC encoding can be divided into two parts as G=[I_k, P], where P is the generator for ECC check word C, i.e., C=d×P. If the j^th chunk of data d_j is written with a new value d_j—new, then the new ECC is:

$\begin{array}{cc}\begin{array}{c}{C}_{\mathrm{new}}=d_{\mathrm{new}}\times P\\ =\left(d+\left[0,\dots ,\left(d_{j\_\mathrm{ol}d}+d_{j\_\mathrm{new}}\right),\dots ,0\right]\right)\times P\\ =C+\left[0,\dots ,\left(d_{j\_\mathrm{ol}d}+d_{j\_\mathrm{new}}\right),\dots ,0\right]\times P\end{array}& \left(1\right)\end{array}$

Equation (1) shows that the generation of new check bits requires only the old value of check bits and the old and new values of the sub-block being modified.

Returning to FIG. 1, the ECC logic 122 is low-latency, low-cost, multi-bit error-correction logic that can compensate for high failure rates in the eDRAM cache 110. The ECC logic 122 implements a strong BCH code with the ability to correct five errors (5EC) and to detect six errors (6ED) (hereafter referred to as a 5EC6ED code). A traditional approach using multi-bit ECC suffers from two prohibitive overheads that limit its applicability. First, building a low-latency decoder for multi-bit ECC codes is extremely costly. Second, the storage overhead of ECC bits is high (around 10% for a 5EC6ED ECC code for a cache line having 64 bytes).

The ECC logic 122 implements a multi-bit error-correcting code with very small area, latency, and power overhead. The ECC logic 122 minimizes embedded DRAM power consumption in low-power operating modes (idle states) without penalizing performance in the normal operating mode. The ECC logic 122 includes a quick ECC logic 104 that is optimized for the cache lines that require little or no correction. The ECC logic 122 includes a high latency ECC logic 106 for cache lines that require complex multi-bit correction. In an embodiment, to minimize the performance impact of processing high latency multi-bit correction, the ECC logic 122 disables lines with multi-bit failures. In another embodiment, the ECC logic 122 leverages the natural spatial locality of the data to reduce the cost of storing the ECC bits.

In one embodiment, the embedded DRAM 110 is a 128 Mega Bytes (MB) last level (Level 3 (L3)) cache included in the processor 100. In a baseline configuration with no error correction capability, the time between refreshes for the embedded DRAM cache 110 is 30 microseconds (us). This results in a significant amount of power consumed even when the Central Processing Unit (CPU) 102 is idle. Power consumed during refresh (refresh power) may be reduced by flushing and power gating the embedded DRAM cache 110 during low-power operating modes, for example, idle states. This, however, causes a significant performance penalty when the CPU 102 wakes up from idle mode (state) because the CPU 102 needs to reload data from external memory (main memory (not shown)) into the embedded DRAM cache 110, thereby incurring a large number of cold start cache misses. Alternatively, refresh power consumption may be reduced by decreasing the refresh frequency, that is, increasing the refresh period (time between refreshes) of the data stored in cache lines in the embedded DRAM cache 110. However, there is a higher number of failures (loss of sate of individual bits (cells)) for each cache line, if refresh frequency is decreased.

The ECC logic 122 implements a code on each 1 KB cache line (5EC6ED), requiring an additional 71 bits (0.87% overhead) for each cache line to store the 5EC6ED code. In an embodiment in which the refresh period is chosen such that no more than 1E-03 (that is, 1/1000) of the cache lines will fail, the baseline configuration with no failure mitigation operates at the baseline refresh time of 30 micro seconds (us). The error correction code logic 122 allows an increase in the refresh period to 440 micro seconds which is almost a 15 times reduction in the refresh period compared to the baseline configuration.

Logic to support a 5EC6ED code is very complex and imposes a long decoding latency penalty, proportional to both the number of error bits corrected and the number of data bits. If full encoding/decoding is required for every access to the cache memory, this can significantly increase cache access latency. In an embodiment of the present invention, error-prone portions of the cache can be disabled, avoiding the high latency of decode during operation.

The error code correction logic 122 includes a quick error correction code (ECC) logic (first error correction logic) 104 and a high-latency error correction code (ECC) logic (second error code correction logic) 106.

The Quick-ECC logic (unit) 104 includes syndrome generation logic and error correction logic for cache lines in eDRAM 110 with zero or one failures. The Quick-ECC logic 104 also classifies cache lines into two groups based on the syndrome: cache lines that require complex multi-bit error correction and cache lines that have less than two, that is, zero or one errors. Cache lines that require multi-bit error correction are forwarded to the high latency ECC processing logic (unit) 106 that performs multi-bit error correction. Cache lines that are corrected by the Quick ECC logic 104 are forwarded to the CPU 102 via L1/L2 cache 124.

In one embodiment, the high latency ECC processing logic 106 performs error correction using software. In another embodiment, the high latency multi-bit ECC processing logic 106 performs multi-bit error correction using a state machine. The combination of the quick ECC logic 104 and the high-latency ECC processing logic 106 allows cache lines in the eDRAM 110 that require one or less error corrections to be immediately corrected and forwarded with low latency to the CPU 102 via the L1/L2 cache 124. Latency increases for forwarding of cache lines in the eDRAM 110 with two or more failures to the CPU 102.

The quick ECC logic 104 in the ECC logic 122 performs a one cycle ECC to correct a single bit error in a cache line in the embedded DRAM 110. The high latency correction logic 106 in the ECC logic 122 performs un-pipelined, high-latency ECC processing to correct multiple bit errors in a cache line.

When a cache line is read from the embedded DRAM 110, it is passed through data buffer 114 to the quick error correction logic 104 together with the tag and ECC associated with the cache line read from the tag/ECC array 108. The tag and ECC are passed through data buffer 116 to the Quick ECC logic 104. A decoder (not shown) in the quick ECC logic 104 generates the syndrome for the received cache line. The generated syndrome includes information on whether the cache line has zero, one, or a higher number of errors. If the cache line has zero or one bit failures, the decoder in the quick ECC logic 104 performs the correction of the one bit failure in a short period of time. In one embodiment, the short period of time can be a single cycle (500 pico seconds (ps)). In other embodiments, the short period of time can be more than one cycle. The period of time is shorter than the time to perform multi-bit error correction by the high-latency ECC processing logic 106.

The high latency associated with handling multi-bit failures may significantly reduce performance. To avoid incurring this high latency, in an embodiment, disabling problematic lines or a mechanism such as bit-fix may be integrated in repair logic 120.

The frequency of errors plays a role in the disable strategy. If there is a low multi-bit error rate, an approach such as disabling cache lines containing multi-bit errors reduces the performance penalty. However, cache line disable results in unacceptable cache capacity loss if multi-bit error rates are high. If there is a high multi-bit error rate, a more complex mechanism such as bit-fix may be used to minimize the capacity lost to disabling cache lines.

In an embodiment, repair logic 120 is coupled between the data buffers 114, 116 and the quick ECC logic 122. With the additional repair logic 120, the performance penalty of multi-bit decoding is incurred only once, that is, the first time an error due to a weak cell in the eDRAM 110 is identified. The repair logic 120 allows the number of errors to be reduced prior to forwarding the cache line to the ECC logic 122. Thus, overall latency is reduced by first using a repair mechanism to fix known errors in a cache line prior to applying ECC to the cache line.

In one embodiment, the repair logic 120 includes bit fix logic. Bit fix logic identifies “broken” bit-pairs and maintains patches to repair the “broken” bit-pairs in the cache line. In an embodiment, the bit fix logic uses a quarter of the ways in a cache set to store positions and fixing bits for failing bits (that is, the correct state (value) for the failing bits in other ways of the set). In low-voltage mode, in an embodiment for a cache memory 110 implemented as an 8-way cache, two of the eight ways are reserved to store defect-correction information to correct the “broken” bit pairs.

The bit fix logic allows defective pairs, that is, groups of 2-bits in the cache line in which at least one bit is defective (due to a logic state retention failure) to be disabled. The bit fix logic maintains a 2-bit “patch” (correct bit state) that can be used to correct the defective 2-bit pair. Repair patterns are stored in selected cache lines in cache memory (eDRAM) 110. During low-voltage operation, the repair patterns (repair pointers and patches) are stored in the cache memory 110. A read or write operation on a cache-line first fetches the repair patterns for the cache line. When reading, repair patterns allow reads to avoid reading data from “broken” bits (defective bits). Using patches from the repair patterns, the cache line is reconstructed before being forwarded to the CPU 102, another cache, or written back to memory. When writing, repair patterns allow writes to avoid writing to failed bits. New patches are written to the repair patterns to reflect new data written to the cache. An embodiment of a repair mechanism (repair logic 120 that uses bit-fix logic has been described. In other embodiments, repair mechanisms other than bit fix can be used to fix known errors prior to applying ECC.

In an embodiment, the cache memory 110 is a 32K 8-way cache having 64B cache lines. Each access to data stored in the cache memory 110 requires an additional access to retrieve the appropriate repair patterns. To access the repair patterns without increasing the number of ports, the bit-fix scheme organizes the cache memory 110 into two banks Two fix-lines are maintained, one in each bank, and each is used for repairing cache-lines in the opposite bank. The repair patterns for three cache lines fit in a single cache line. Thus a single fix-line (a cache line storing repair patterns) for every three cache lines is maintained. A fix-line is assigned to the bank opposite to the three cache lines that use its repair patterns. This allows a cache line to be fetched in parallel with its repair patterns without increasing the number of cache ports.

On a cache hit, the data line is read from one bank in the cache memory 110 and a fix-line is read from another bank in the cache memory 110. The data line passes through ‘n’ bit shift stages, where ‘n’ represents the number of defective bit pairs. Each stage removes a defective pair, replacing it with the fixed pair. As the fix-line may also contain broken bits, SECDED ECC is applied to correct the repair patterns in the fix line before they are used. After the repair patterns have been fixed, they are used to correct the data-line. Repairing a single defective pair consists of three parts. First, SECDED ECC repairs any defective bits in the repair pattern. Second, a defect pointer identifies the defective pair. Third, after the defective pair has been removed, a patch reintroduces the missing correct bits into the cache line.

FIG. 2 is a block diagram of a system 200 including an embodiment of a Recently Accessed Line Table (RALT) 112 and the embedded DRAM cache 110 and ECC logic 122 shown in FIG. 1 illustrating a fast access to a cache line in the eDRAM cache 110.

A cache line size greater than 64 bytes is used to reduce the memory storage required to store multi-bit ECC codes. In an embodiment, the eDRAM cache 110 is a Level 3 (L3) cache which is 128 MB embedded DRAM and the size of a cache line 202 is 1024 Bytes (1 Kilobytes (KB)). A Level 2 (L2) cache/Level 1 (L1) cache 124 has a 64 Byte (B) cache line (referred to as a sub-block of the L3 cache line). Most writes to the L3 eDRAM cache 110 are in the form of smaller 64 Byte sub-blocks generated at lower-level (L1 or L2) cache memories 124 or fetched from non-cache memory (main memory/external memory (not shown)).

To modify a 64B sub-block 204 in a 1 KB cache line 202, a read-modify-write operation is performed by the CPU 102 in order to compute the ECC code. First, the 64B sub-block 204 that is being overwritten is read from the eDRAM cache 110 together with the ECC code 208 for the entire 1 KB cache line 202. The old data, old ECC code, and new data are used to compute the new ECC 208 for the entire 1 KB cache line 202. The new 64B sub-block 204 and a new ECC code 208 are written back to the L3 eDRAM cache 110. However, the entire 1 KB cache line 202 is not read in order to compute the new ECC 208 as will be discussed later.

Most reads from L3 cache 110 are performed to provide cache lines for allocation in lower-level (L1 and L2) caches 124. Processing any sub-block 204 of a cache line 202 requires the ECC 208 to be processed with the entire data word (a 1 KB cache line) 202 that it protects. As each 64B sub-block 204 in the 1 KB cache line 202 needs to be checked, each reference to a 64B sub-block 204 is accompanied by a reference to the surrounding 64B sub-blocks 204. Thus, any read of the L3 embedded DRAM cache 110 accesses all 16 64-bit sub-blocks 204 in the 1 KB cache line 202, in addition to the ECC 208 (per cache line) that all of the sub-blocks 204 share in the cache line 202. For example, in order to read only eight of the 16 sub-blocks 204 in one 1 KB cache line 202, all 16 sub-blocks 204 are read eight times, for a total of 128 separate sub-block reads. This large number of additional sub-block reads results in a substantial increase in dynamic power consumption and a reduction in the useful cache bandwidth provided by the eDRAM cache 110.

The majority of eDRAM failures are due to retention failures because as already discussed, the eDRAM cache 110 needs to be periodically refreshed to maintain the current state of each memory cell. In an embodiment, the retention time is 30 micro seconds (us), and each read of a particular cache line automatically implies a refresh of that cache line. Thus, retention failures should not occur for 30 us in a particular cache line after that cache line has been read. This observation allows the number the superfluous reads to be minimized. The RALT 112 is used to track cache lines that have been referenced (read) within the last 30 us.

The first read to a cache line 202 in the eDRAM cache 110 results in all of the sub-blocks 204 in the cache line 202 being read and checked for errors. The address of the cache line 202 that is read is stored in a RALT entry 206 in the RALT 112. The stored address indicates that the cache line 202 has recently been read and checked and thus should remain free from retention errors for the next 30 us. While the address of the read cache line is stored in the RALT 112, any subsequent reads of sub-block from that cache line 202 can forgo ECC processing and thus avoid reading the ECC 208 associated with the cache line 202 and other sub-blocks 204 in the cache line 202. The RALT 112 ensures that none of its entries 206 have been stored for more than 30 us by dividing each 30 us time period into a plurality of equal “cache line read” periods. Entries 206 that are allocated in the RALT 112 during each period are marked with a period identifier 214 identifying the sub-refresh period. Transitions between sub-refresh periods results in all RALT entries previously allocated in one of the plurality of “cache line read” periods to be invalidated (as indicated by the state of the “valid” field associated with the entry 206 in the RALT).

Each entry 206 in the RALT 112 includes the following fields: a line address field 209 to identify the cache line that the entry is associated with; a valid field 212, a period identifier field 214 to indicate in which period the line was allocated; and a parity field 211 that includes one parity bit for each sub-block in the cache line. In an embodiment the period identifier field 214 has two bits to indicate which of four periods (P0, P1, P2, P3) the cache line was allocated and the parity field 211 has 16-bits, one per 64B sub-block in the cache line. The RALT 112 is direct mapped, but supports a CAM (Content Addressable Memory) invalidate on the period field 214 to allow bulk invalidates of entries 206 in the RALT 112 during period transitions.

The first time a sub-block 204 is read, the entire ECC 208 is also read along with each sub-block in the 1 KB cache line 202 to allow ECC processing for a single 64B sub-block 204. The entry 206 associated with the cache line 202 in the RALT 112 is updated with the line address of the referenced cache line 202, a period identifier, and a single parity bit for each sub-block 204 in the cache line 202. After the first hit to a cache line 202, future accesses to the same cache line 202 within the refresh period do not require ECC processing.

The first read to a cache line causes all sub-blocks in the line to be read and checked for failures. The address of the line is then stored in the RALT to indicate that it has recently been checked and will remain free from retention failures for the next 30 usec. As long as the address of the line is stored in the RALT, any sub-block reads from the line can forgo ECC processing and thus avoid reading the ECC code and other sub-blocks in the line.

To operate correctly, the RALT 112 ensures that none of its entries are more than 30 us old. To guarantee this, a counter 216 is used to measure the passage of each 30 us period. Each 30 us period is divided into four equal sub-periods (P0, P1, P2, P3). Entries allocated in the RALT 112 during each period are marked with a 2 bit identifier to specify the allocation sub-period which can be determined by checking the current value of the counter. For example, the passage of 30 us in a 2 GHz processor 100 can be measured using a counter 216 that increments every cycle counting to 60000. Counter values between 0-15000 for example correspond to sub-period P0, 15001-30000 correspond to sub-period P1, 30001-45000 correspond to sub-period P2, and 45001-60000 correspond to sub-period P3. When the counter 216 reaches 60000 it resets to 0, resulting in a transition from P3 to P0. Each sub-period transition can cause the invalidation of some or all of the RALT entries allocated during the previous instance of that sub-period. For example, a transition from sub-period P0 to sub-period P1 will result in all RALT entries previously allocated in sub-period P1 to be invalidated.

FIG. 3 is a block diagram of the system shown in FIG. 2 illustrating a subsequent read of a cache line within the refresh period. In most cases, only the requested 64B sub-block 204 is read. Parity for the 64B sub-block 204 is computed and compared to the parity 211 for that 64B sub-block 204 of the cache line 202 stored in the RALT 112. If there is a match, the inference is that the 64B sub-block 204 is valid and the 64B sub-block 204 is forwarded to the requesting cache 124 or processor 102. A parity mismatch is treated as a RALT miss and the entire 1 KB cache line 202 is read. The RALT 112 is used to track recently accessed cache lines 202 to avoid reading the entire 1 KB cache line 202 on every cache read, thus minimizing dynamic power.

FIG. 4A is a block diagram illustrating an embodiment of an ECC encoder 400 included in the quick ECC logic 104 shown in FIG. 1. BCH codes are a large class of multi-bit error-correcting codes which can correct both highly concentrated and widely scattered errors. In general, each BCH code is a linear block code defined over a finite Galois Field GF(2^m) with a generator polynomial, where 2^m represents the maximum number of code word bits.

The ECC encoder (encoding logic) 400 takes the k-bit input data word d and uses a pre-defined encoder matrix G to generate the corresponding code word u (u=d×G). As BCH is a systematic code, the original k-bit data is retained in the code word u(x), and is followed by r check bits.

FIG. 4B is a block diagram illustrating an embodiment of an ECC decoder (decoding logic) 402 included in the quick ECC logic shown in FIG. 1. The decoding logic 402 detects and corrects any errors in the received code word u(x) to recover the original value of data. The decoding logic 402 includes syndrome generation logic 404, error classification logic 406 and error correction logic 408.

The syndrome generation logic 404 first computes a syndrome S by multiplying v (a code word with error e, such that v=u+e) with the transpose of a pre-defined H-matrix (S=v×H^T). The G and H matrices are constructed in such a way that G×H^T=0. The general form of H-matrix is as follows:

$\begin{array}{cc}H=\left[\begin{array}{c}\mathrm{Parity}\\ H_1\\ H_3\\ \dots \\ H_{2t-1}\end{array}\right]=\left[\begin{array}{cccccc}1& 1& 1& 1& \dots & 1\\ 1& \alpha & {\alpha }^2& {\alpha }^3& \dots & {\alpha }^{\left(n-1\right)}\\ 1& {\alpha }^3& {\alpha }^6& {\alpha }^9& \dots & {\alpha }^{3\left(n-1\right)}\\ ⋮& ⋮& ⋮& ⋮& \dots & ⋮\\ 1& {\alpha }^{\left(2t-1\right)}& {\alpha }^{2^{*}\left(2t-1\right)}& {\alpha }^{3^{*}\left(2t-1\right)}& \dots & {\alpha }^{{\left(2t-1\right)}^{*}\left(n-1\right)}\end{array}\right]& \left(2\right)\end{array}$

In the finite field GF(2^m), each element αⁱ can be represented as a polynomial of a with a degree less than m, or simply a vector with m binary coefficients of the polynomial. Therefore, the H matrix can be expanded into a binary matrix with (t*m+1) rows, where t is the maximum number of errors that the code can correct. Since S=v×H^T, S also has t*m+1 bits, which can be divided into multiple components [Parity, S₁, S₃, S_2t-1].

The error classification logic uses the syndrome S to detect if the code word has any errors. Since:

S=v×H^T=(u+e)×H^T=(d×G+e)×H^T=d×(G×H^T)+e×H^T=e×H^T  (3)

Therefore, in case of zero errors, S=0 and the following equation would hold true:

Parity=S₁=S₃= . . . =S_2t-1=0  (4)

No errors in the code word lead to a syndrome value of zero, as shown in equation (3). This case can be detected by performing a logical OR of all the syndrome bits. This requires ceil(log₂tm) 2-input gate delays.

The error correction logic uses the syndrome value to pinpoint the locations of corrupted bits, if the above equation is not satisfied.

Let the error locations in e be denoted as [j₁, j₂, j_t], then each syndrome component S_i can be specified as:

S_i=α^j1*i+α^j2*i+ . . . +α^jt*i  (5)

The correction logic implements the following three steps:

Step 1: Determine the coefficients of error location polynomial σ(x), where σ(x) is defined such that the roots of σ(x) are given by the inverse of error elements α^j1, α^j2, . . . , α^jt respectively,

σ(x)=1+σ₁x+ . . . +σ_tx^t=(1−α^j1x)(1−α^j2x) . . . (1−α^jtx)  (6)

Step 1 of error correction is based on a t-step iterative algorithm, where each iteration involves a Galois Field inversion, which alone takes 2 m operations

Step 2: Solve the roots of σ(x), which are the error locations. When polynomial σ(x) is determined, each field element α^j is substituted into the polynomial. Those elements which make the polynomial equal to zero are the roots. The implementation of Step 2 can either take n-cycles with one circuit, or a single cycle with n parallel circuits. Either way, the base circuit is O(t*m²).

Step 3: Calculate the correct value for data bits. This is done by simply flipping the bits at error locations.

In the case of a single-bit error, the syndrome exactly matches the H-matrix column that corresponds to the error bit. Therefore, a single-bit error can be detected by comparing each column of the H-matrix with the syndrome. This correction is significantly faster than the general case oft-bit correction (with t>1) because it does not require Step 1 and most of the Step 2 of the error correction logic. All the syndrome components do not need to be matched with entire H-matrix columns. All that is needed is to compare S₁ to each column in H₁ (defined in equation (1)) and verify that the following equation is satisfied:

[(parity=1)&(S₁³==S₃)&(S₁⁵==S₅)& . . . &(S₁^2t-1==S_2t-1)]==1  (7)

To minimize latency, the comparison of S₁ with H₁ and all the comparisons in equation (7) can proceed in parallel.

FIG. 5 is a flow graph illustrating an embodiment of a method for using the system 100 shown in FIG. 1 according to the principles of the present invention.

At block 500, if the cache line address (addr) is associated with a RALT entry 206 in the Recently Accessed Line Table 112, the cache line has been recently accessed and no error checking is required, the cache line address is forwarded to the CPU 102 via the L1/L2 cache 124. If not, processing continues with block 502.

At block 502, the cache line address (addr) is stored in a line address field 209 in a RALT entry 206 the RALT Table 112 as discussed earlier in conjunction with FIG. 2. Data stored in the cache line in cache memory 110 and the Tag/ECC stored in the Tag/ECC array 118 corresponding to the address is read and forwarded through data buffers 114, 116. Processing continues with block 504.

At block 504, in an embodiment that includes repair logic 120, processing continues with block 512 to repair the cache line. In an embodiment that does not include repair logic, processing continues with block 506.

At block 506, quick ECC is performed by quick ECC logic 104 to determine if there are errors in the cache line. Processing continues with block 508.

At block 508, if there are more than two errors in the cache line to be corrected, processing continues with block 514. If there are less than two errors, the error is corrected by the quick ECC logic 104 and processing continues with block 510.

At block 510, the corrected cache line data is forwarded to the CPU 102 via L1/L2 cache 124.

At block 512, the cache line data read from cache memory 110 and forwarded through data buffers 114, 116 is repaired as discussed earlier. Processing continues with block 506.

At block 514, the Hi ECC logic corrects the multi-bit error in the cache line and processing continues with block 510.

FIG. 6 is a block diagram of a system 600 that includes an embodiment of the processor 100 shown in FIG. 1. The system 600 includes a processor 100 with embedded cache memory, a Memory Controller Hub (MCH) 602 and an Input/Output (I/O) Controller Hub (ICH) 604. The MCH 602 includes a memory controller 606 that controls communication between the processor 601 and external memory (main memory) 610. The processor 100 and MCH 602 communicate over a system bus 616.

The CPU 102 may be any one of a plurality of processors such as a single core Intel® Pentium IV® processor, a single core Intel Celeron processor, an Intel® XScale processor or a multi-core processor such as Intel® Pentium D, Intel® Xeon® processor, or Intel® Core® Duo processor or any other type of processor.

The memory 610 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronized Dynamic Random Access Memory (SDRAM), Double Data Rate 2 (DDR2) RAM or Rambus Dynamic Random Access Memory (RDRAM) or any other type of memory.

The ICH 604 may be coupled to the MCH 602 using a high speed chip-to-chip interconnect 614 such as Direct Media Interface (DMI). DMI supports 2 Gigabit/second concurrent transfer rates via two unidirectional lanes.

The ICH 604 may include a storage Input/Output (I/O) controller for controlling communication with at least one storage device 612 coupled to the ICH 604. The storage device may be, for example, a disk drive, Digital Video Disk (DVD) drive, Compact Disk (CD) drive, Redundant Array of Independent Disks (RAID), tape drive or other storage device. The ICH 604 may communicate with the storage device 612 over a storage protocol interconnect 618 using a serial storage protocol such as, Serial Attached Small Computer System Interface (SAS) or Serial Advanced Technology Attachment (SATA).

It will be apparent to those of ordinary skill in the art that methods involved in embodiments of the present invention may be embodied in a computer program product that includes a computer usable medium. For example, such a computer usable medium may consist of a read only memory device, such as a Compact Disk Read Only Memory (CD ROM) disk or conventional ROM devices, or a computer diskette, having a computer readable program code stored thereon.

While embodiments of the invention have been particularly shown and described with references to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of embodiments of the invention encompassed by the appended claims.

Claims

1. An apparatus comprising:

a cache memory; and

an error correction logic to receive data stored in a cache line in the cache memory, the error correction logic comprising: a first error correction logic to generate a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line; and a second error correction logic to receive the cache line from the first error correction logic only if the cache line has greater than one error, the second error correction logic to perform multi-bit error correction for the received cache line.

2. The apparatus of claim 1, further comprising:

repair logic, the repair logic to fix known errors in the cache line prior to forwarding the cache line to the error correction logic.

3. The apparatus of claim 1, wherein the cache memory is volatile memory.

4. The apparatus of claim 1, wherein the first error correction logic includes a decoder to perform correction in a shorter period of time than the multi-bit error correction.

5. The apparatus of claim 1, wherein the first error correction logic includes syndrome generation logic and error correction logic for cache lines with zero or one failures.

6. The apparatus of claim 1, further comprising:

a Recently Accessed Line Table (RALT) coupled to the address bus of the cache memory, the RALT to determine if the addressed cache line has been accessed within a current refresh time period of the volatile cache memory.

7. The apparatus of claim 6, wherein the RALT is used to track recently accessed lines.

8. The apparatus of claim 1, wherein the first error correction logic to perform error correction for the single error in the received cache line.

9. A method comprising:

storing data in a cache memory;

receiving, by an error correction logic data stored in a cache line in the cache memory, the error correction logic comprising a first error correction logic and a second error correction logic;

generating, by the first error correction logic, a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line;

forwarding the cache line, by the first error correction logic to a second error correction logic only if the cache line has greater than one error; and

performing, by the second error correction logic, multi-bit error correction for the received cache line.

10. The method of claim 9, further comprising:

repairing, by repair logic, known errors in the cache line prior to forwarding the cache line to the error correction logic.

11. The method of claim 9, further comprising:

performing, by the first error correction logic, correction in a shorter period of time than the multi-bit error correction.

12. The method of claim 11, further comprising:

determining, by a Recently Accessed Line Table (RALT) coupled to the address bus of the cache memory, if the addressed cache line has been accessed within a current refresh time period of the cache memory.

13. The method of claim 12, further comprising:

tracking, by the RALT, recently accessed cache lines.

14. The method of claim 9, further comprising:

performing, by the first error correction logic, error correction for the single error in the received cache line.

15. An article including a machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:

storing data in a cache memory;

receiving, by an error correction logic data stored in a cache line in the cache memory, the error correction logic comprising a first error correction logic and a second error correction logic;

generating, by the first error correction logic, a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line;

forwarding the cache line, by the first error correction logic to a second error correction logic only if the cache line has greater than one error; and

performing, by the second error correction logic, multi-bit error correction for the received cache line.

16. The article of claim 15 further comprising:

repairing, by repair logic, known errors in the cache line prior to forwarding the cache line to the error correction logic.

17. The article of claim 15, further comprising:

performing, by the first error correction logic, correction in a shorter period of time than the multi-bit error correction.

18. The article of claim 15, further comprising:

determining, by a Recently Accessed Line Table (RALT) coupled to the address bus of the cache memory, if the addressed cache line has been accessed within a current refresh time period of the cache memory.

19. The article of claim 15, further comprising:

performing, by the first error correction logic, error correction for the single error in the received cache line.

20. A system comprising:

an external memory; and

a processor, the processor comprising: a cache memory to store data read from the external memory; and an error correction logic to receive data stored in a cache line in the cache memory, the error correction logic comprising: a first error correction logic to generate a syndrome for the received cache line read from the cache memory to determine a number of errors in the cache line; and a second error correction logic to receive the cache line from the first error correction logic only if the cache line has greater than one error, the second error correction logic to perform multi-bit error correction for the received cache line.

21. The system of claim 20, further comprising:

repair logic, the repair logic to fix known errors in the cache line prior to forwarding the cache line to the error correction logic.

22. The system of claim 20, wherein the first error correction logic includes a decoder to perform correction in a shorter period of time than the multi-bit error correction and syndrome generation logic and error correction logic for cache lines with zero or one failures.