Patents by Inventor Alain Blosse
Alain Blosse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8547121Abstract: A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.Type: GrantFiled: April 29, 2010Date of Patent: October 1, 2013Assignee: Silicor Materials Inc.Inventors: Kamel Ounadjela, Marcin Walerysiak, Anis Jouini, Matthias Heuer, Omar Sidelkheir, Alain Blosse, Fritz Kirscht
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Patent number: 8404970Abstract: A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes an active region located on the front surface of the substrate, formed for example by a phosphorous diffusion step. The back surface includes a doped region, the doped region having the same conductivity as the substrate but with a higher doping level. Contact grids are formed, for example by screen printing. Front junction isolation is accomplished using a laser scribe.Type: GrantFiled: June 15, 2009Date of Patent: March 26, 2013Assignee: Silicor Materials Inc.Inventors: Martin Kaes, Peter Borden, Kamel Ounadjela, Andreas Kraenzl, Alain Blosse, Fritz G. Kirscht
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Patent number: 8298850Abstract: A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes an active region located on the front surface of the substrate, formed for example by a phosphorous diffusion step. After removing the PSG, assuming phosphorous diffusion, and isolating the front junction, dielectric layers are deposited on the front and back surfaces. Contact grids are formed, for example by screen printing. Prior to depositing the back surface dielectric, a metal grid may be applied to the back surface, the back surface contact grid registered to, and alloyed to, the metal grid during contact firing.Type: GrantFiled: June 15, 2009Date of Patent: October 30, 2012Assignee: Silicor Materials Inc.Inventors: Martin Kaes, Peter Borden, Kamel Ounadjela, Andreas Kraenzl, Alain Blosse, Fritz G. Kirscht
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Patent number: 8080453Abstract: A semiconductor structure includes a semiconductor substrate, a gate layer containing silicon on the semiconductor substrate, a metallic layer on the gate layer, and a nitride layer on the metallic layer. The gate layer contains a P+ region and an N+ region.Type: GrantFiled: June 28, 2002Date of Patent: December 20, 2011Assignee: Cypress Semiconductor CorporationInventors: Alain Blosse, Krishnaswamy Ramkumar
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Publication number: 20100327890Abstract: A quality control process for determining the concentrations of boron and phosphorous in a UMG-Si feedstock batch is provided. A silicon test ingot is formed by the directional solidification of molten UMG-Si from a UMG-Si feedstock batch. The resistivity of the silicon test ingot is measured from top to bottom. Then, the resistivity profile of the silicon test ingot is mapped. From the resistivity profile of the silicon test ingot, the concentrations of boron and phosphorous of the UMG-Si silicon feedstock batch are calculated. Additionally, multiple test ingots may be grown simultaneously, with each test ingot corresponding to a UMG-Si feedstock batch, in a multi-crucible crystal grower.Type: ApplicationFiled: April 29, 2010Publication date: December 30, 2010Applicant: CaliSolar, Inc.Inventors: Kamel Ounadjela, Marcin Walerysiak, Anis Jouini, Matthias Heuer, Omar Sidelkheir, Alain Blosse, Fritz Kirscht
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Publication number: 20100310445Abstract: A process control method for UMG-Si purification by performing a directional solidification of molten UMG-Si to form a silicon ingot is described. The ingot is divided into bricks and the resistivity profile of each silicon brick is mapped. A crop line for removing the impurities concentrated and captured in the ingot during the directional solidification is calculated based on the resistivity map. The concentrated impurities are then removed by cropping each brick along that brick's calculated crop line.Type: ApplicationFiled: February 10, 2010Publication date: December 9, 2010Applicant: CaliSolar, Inc.Inventors: Kamel Ounadjela, Marcin Walerysiak, Anis Jouini, Matthias Heuer, Omar Sidelkheir, Alain Blosse, Fritz Kirscht
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Publication number: 20100275984Abstract: A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes an active region located on the front surface of the substrate, formed for example by a phosphorous diffusion step. The back surface includes a doped region, the doped region having the same conductivity as the substrate but with a higher doping level. Contact grids are formed, for example by screen printing. Front junction isolation is accomplished using a laser scribe.Type: ApplicationFiled: June 15, 2009Publication date: November 4, 2010Applicant: Calisolar, Inc.Inventors: Martin Kaes, Peter Borden, Kamel Ounadjela, Andreas Kraenzl, Alain Blosse, Fritz G. Kirscht
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Publication number: 20100275995Abstract: A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes a back surface contact grid and an overlaid blanket metal reflector. A doped amorphous silicon layer is interposed between the contact grid and the blanket layer.Type: ApplicationFiled: June 15, 2009Publication date: November 4, 2010Applicant: Calisolar, Inc.Inventors: Martin Kaes, Peter Borden, Kamel Ounadjela, Andreas Kraenzl, Alain Blosse, Fritz G. Kirscht
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Publication number: 20100275983Abstract: A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes an active region located on the front surface of the substrate, formed for example by a phosphorous diffusion step. After removing the PSG, assuming phosphorous diffusion, and isolating the front junction, dielectric layers are deposited on the front and back surfaces. Contact grids are formed, for example by screen printing. Prior to depositing the back surface dielectric, a metal grid may be applied to the back surface, the back surface contact grid registered to, and alloyed to, the metal grid during contact firing.Type: ApplicationFiled: June 15, 2009Publication date: November 4, 2010Applicant: Calisolar, Inc.Inventors: Martin Kaes, Peter Borden, Kamel Ounadjela, Andreas Kraenzl, Alain Blosse, Fritz G. Kirscht
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SOLAR CELL AND FABRICATION METHOD USING CRYSTALLINE SILICON BASED ON LOWER GRADE FEEDSTOCK MATERIALS
Publication number: 20090223549Abstract: Formation of a solar cell device from upgraded metallurgical grade silicon which has received at least one defect engineering process and including a low contact resistance electrical path. An anti-reflective coating is formed on an emitter layer and back contacts are formed on a back surface of the bulk silicon substrate. This photovoltaic device may be fired to form a back surface field at a temperature sufficiently low to avoid reversal of previous defect engineering processes. The process further forms openings in the anti-reflective coating and a low contact resistance metal layer, such as nickel layer, over the openings in the anti-reflective coating. The process may anneal the low contact resistance metal layer to form n-doped portion and complete an electrically conduct path to the n-doped layer. This low temperature metallization (e.g., <700° C.) supports the use of UMG silicon for the solar device formation without the risk of reversing earlier defect engineering processes.Type: ApplicationFiled: March 10, 2008Publication date: September 10, 2009Applicant: CaliSolar, Inc.Inventors: Kamel Ounadjela, Jean Patrice Rakotoniaina, Martin Kaes, Dirk Zickermann, Alain Blosse, Abdellatif Zerga, Matthias Heuer, Fritz Kirscht -
Patent number: 7396773Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.Type: GrantFiled: December 6, 2002Date of Patent: July 8, 2008Assignee: Cypress Semiconductor CompanyInventors: Alain Blosse, Krishnaswamy Ramkumar
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Patent number: 7323411Abstract: In one embodiment, a selective tungsten deposition process includes the steps of pre-flowing silane into a deposition chamber, pumping down the chamber, and then selectively depositing tungsten on a silicon surface. The silane pre-flow helps minimize silicon consumption, while the pump down helps prevent loss of tungsten selectivity to silicon.Type: GrantFiled: September 22, 2004Date of Patent: January 29, 2008Assignee: Cypress Semiconductor CorporationInventor: Alain Blosse
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Patent number: 7256083Abstract: A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.Type: GrantFiled: June 28, 2002Date of Patent: August 14, 2007Assignee: Cypress Semiconductor CorporationInventors: Alain Blosse, Krishnaswamy Ramkumar
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Patent number: 7189652Abstract: A method of forming a semiconductor structure comprises oxidizing a stack, to form sidewall oxide in contact with sides of the stack. The stack is on a semiconductor substrate, the stack includes a gate layer, comprising silicon; a metallic layer, on the gate layer; and an etch-stop layer, on the metallic layer. The sidewall oxide in contact with the metallic layer is thinner than the sidewall oxide in contact with the gate layer.Type: GrantFiled: December 6, 2002Date of Patent: March 13, 2007Assignee: Cypress Semiconductor CorporationInventors: Alain Blosse, Sundar Narayanan, Krishnaswamy Ramkumar
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Patent number: 7151048Abstract: A method of forming a semiconductor structure comprises forming sidewall oxide on a stack, by rapid thermal oxidation. The stack is on a substrate and comprises (i) a first layer comprising silicon, (ii) a second layer, comprising silicon and tungsten, on the first layer, and (iii) a capping layer, on the second layer. The sidewall oxide in contact with the second layer is at most 50% thicker than the sidewall oxide in contact with the first layer.Type: GrantFiled: March 14, 2002Date of Patent: December 19, 2006Assignee: Cypress Semiconductor CorporationInventor: Alain Blosse
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Patent number: 7018942Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.Type: GrantFiled: November 15, 2004Date of Patent: March 28, 2006Assignee: Cypress Semiconductor CorporationInventors: Mira Ben-Tzur, Krishnaswamy Ramkumar, Alain Blosse, Fuad Badrieh
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Patent number: 6979640Abstract: A method of making a semiconductor structure comprises forming a hole through a first dielectric layer; followed by forming a hole through an etch-stop layer, to expose a first conducting layer. The thickness of the etch-stop layer is at least one-half the smallest line width of the first conducting layer.Type: GrantFiled: March 29, 2002Date of Patent: December 27, 2005Assignee: Cypress Semiconductor CorporationInventors: Alain Blosse, Sanjay Thekdi
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Patent number: 6902993Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.Type: GrantFiled: March 28, 2003Date of Patent: June 7, 2005Assignee: Cypress Semiconductor CorporationInventors: Alain Blosse, Krishnaswamy Ramkumar, Prabhuram Gopalan
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Patent number: 6887784Abstract: A method of making a structure, includes filling a via hole with a conductive material, to form a via. The via hole passes through an etch-stop opening. In both directions along a first axis dielectric material is present between the via hole and edges of the etch-stop layer, and in both directions along a second axis, perpendicular to said first axis, dielectric material is not present between the via hole and edges of the etch-stop layer.Type: GrantFiled: June 19, 2002Date of Patent: May 3, 2005Assignee: Cypress Semiconductor CorporationInventor: Alain Blosse
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Patent number: 6869850Abstract: In one embodiment, a transistor comprises raised structures over a source region and a drain region. The raised source structures may comprise selectively deposited metal, such as selective tungsten. A self-aligned contact structure formed through a dielectric layer may provide an electrical connection between an overlying structure (e.g., an interconnect line) and the source or drain region. The transistor may further comprise a gate stack having a capping layer over a metal.Type: GrantFiled: December 20, 2002Date of Patent: March 22, 2005Assignee: Cypress Semiconductor CorporationInventors: Alain Blosse, Krishnaswamy Ramkumar