Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: A method of forming a semiconductor structure comprises forming a nitride layer on a stack, and etching the nitride layer to form spacers in contact with sides of the stack. The stack is on a semiconductor substrate, the stack comprises (i) a gate layer, comprising silicon, (ii) a metallic layer, on the gate layer, and (iii) an etch-stop layer, on the metallic layer. The forming is by CVD with a gas comprising SixL2x, L is an amino group, and X is 1 or 2.

Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

Abstract: The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.

Abstract: A semiconductor structure, comprises a semiconductor substrate, a gate layer on the semiconductor substrate, a metallic layer on the gate layer, and an etch-stop layer on the metallic layer. A distance between the substrate and a top of the etch-stop layer is a gate stack height, and the gate stack height is at most 2700 angstroms. In addition, the etch-stop layer has a thickness of at least 800 angstroms.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.

Abstract: The invention concerns a method for simultaneously forming a metallization and contact structure in an integrated circuit. The method involves the steps of etching a trench dielectric layer of a composite structure having a semiconductor substrate with an active region, a gate structure thereon, at least one dielectric spacer adjacent to the gate structure, a contact dielectric layer over the semiconductor substrate, the gate structure and the dielectric spacer, an etch stop layer over the contact dielectric layer, and a trench dielectric layer over the etch stop layer, to form a trench in the trench dielectric under etch conditions which do not substantially etch the etch stop layer; thereafter, forming an opening in the etch stop layer and the contact dielectric layer by etching under conditions which do not damage the gate structure to expose the active region; and depositing a conductive material into the opening and the trench.