Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

Abstract: Techniques regarding one or more VFETs operably coupled to bottom contacts with low electrical resistance are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a vertical field-effect transistor device that can comprise a semiconductor fin positioned on a source/drain region, which can comprise a semiconductor substrate. The apparatus can also comprise a metal contact layer positioned on the source/drain region and at least partially surrounding a base of the semiconductor fin. Further, the metal contact layer can be in electrical communication with the source/drain region.

Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

Abstract: This disclosure describes techniques for delivering high-accuracy and high-precision clock synchronization in heterogeneous distributed computer clusters. For example, the disclosure describes a synchronization engine that sets efficient clock synchronization processes based on a cluster node's characteristics, pricing, precision, geolocation, and/or cluster topology, while in some cases using a combination of master clock data with internal atomic clocks of computers. The techniques described herein integrate the synchronization engine into a time synchronization process that may provide stability, versatility, precision and cost balance using technical improvements for characterizing timing system delivery channels.

Abstract: A multi-layer device comprising a barrier or adhesion layer located on a portion of a first top surface of a first layer, a conductive metal layer located on barrier or adhesion layer; and a dielectric layer located on top of the first layer, wherein the dielectric layer is in direct contact with the sidewall of the conductive metal layer.

Abstract: Integrated chips and methods of forming lines in the same include forming first lines on a underlying substrate. Conformal dielectric spacers are formed on sidewalls of the first lines. Second lines are formed on the underlying substrate, in open areas between the dielectric spacers.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.

Abstract: A vehicle interior component is disclosed. The component may comprise a base comprising a surface and a support comprising a surface and configured to move between raised and lowered positions. The surfaces of the support and base may comprise a substantially continuous surface when the support is in the raised position. The support may descend into the base to provide a cavity. The component may comprise a light source to illuminate a border around the support and walls of the cavity. The component may comprise a mechanism to move the support. The support may comprise a switch to send a signal to the mechanism to move the support. The mechanism may comprise an adaptive volume mechanism. The component may comprise a wireless charger configured to send a signal to a controller to move the support. The component may comprise at least one of a console; armrest; instrument panel; door.

Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.

Abstract: A sustaining device is described for prolonging the vibration of the strings of a stringed musical instrument, such as an electric guitar having two or three electromagnetic pickups. The pickups are all low impedance transducers that can function either as pickups or driver transducers, depending on whether they are connected to the input of the instrument pickup amplifier or to the output of the sustainer amplifier, respectively. When a transducer is being used as a sustainer driver, it cannot be simultaneously used as a pickup. Different methods of selecting transducers to function as pickups or drivers are described. The transducers, having only hundreds of wire turns instead of the usual thousands of turns for common pickups, have a flat audio frequency response that can be modified to produce a multitude of common pickup sounds by manipulating the transducer resonance frequency, bandwidth, and amplifier gain.

Abstract: A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.

Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.

Abstract: A vehicle interior component is disclosed. The component may comprise a base comprising a surface and a support comprising a surface and configured to move between raised and lowered positions. The surfaces of the support and base may comprise a substantially continuous surface when the support is in the raised position. The support may descend into the base to provide a cavity. The component may comprise a light source to illuminate a border around the support and walls of the cavity. The component may comprise a mechanism to move the support. The support may comprise a switch to send a signal to the mechanism to move the support. The mechanism may comprise an adaptive volume mechanism. The component may comprise a wireless charger configured to send a signal to a controller to move the support. The component may comprise at least one of a console; armrest; instrument panel; door.

Abstract: An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.

Abstract: The present invention relates to a dispenser module for converting preexisting analog systems into a customizable digital system. According to an illustrative embodiment of the present disclosure, a user can utilize preexisting analog equipment to operate and control a dispenser module. A squib is electrically connected to a logic circuit such that the normal “firing” of the original payload at that location will cause a change in the state of the electrical circuit. Because there are multiple payload allocations within one module, this allows electrical communication with individual/select payload devices by an operator. Payloads in the module can be quickly swapped in and out without making any changes to the vehicle.

Abstract: A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.

Abstract: A method to enforce compliance with multiple-person-control rules in a secure-computing system to protect against the insider threat. The method can be patched onto an existing secure computer systems to provide granular control of any type of resource request. Existing user-user access controls are configured to prevent users from gaining unfettered access. Tasks requiring higher privilege, such as system administration, are performed under the present method of multiple-person controls, using digital signatures of resource requests to provide a separate layer of protection. A script running with sufficient privilege executes resource requests requiring privilege elevation, but only after validating a first digital signature signed by a requester and validating one or more additional digital signatures signed by reviewers. To detect playback attacks, a nonce can be included in the signed message and compared with nonce values from previously processed resource requests.

Abstract: A method of generating a look-up table, LUT, for constructing a dewarped B-scan image from A-scans of a cropped part of a sequence of acquired OCT A-scans, the LUT associating each of a plurality of pixel arrays that are to form the dewarped B-scan image with a respective A-scan in the cropped part. The method comprises: using an indication of a spatial distribution of scan locations of A-scans to determine a dewarp function for selecting, from among acquired A-scans, A-scans having uniformly spaced scan locations; using the function and cropping information, in accordance with which the cropped part is cropped from the acquired sequence, to select, for each array, a respective A-scan from the sequence such that A-scans are selected from the cropped part and have uniformly spaced scan locations; and storing, for each array, a respective pixel array identifier in association with a respective identifier of the selected A-scan.

Abstract: An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.