Abstract: A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.

Abstract: A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.

Abstract: In a memory array having a minimum unit of erase of a block, a scratch pad block is used to store data that is later written to another block. The data may be written to the scratch pad block with a low degree of parallelism and later written to another location with a high degree of parallelism so that it is stored with high density. Data may be temporarily stored in the scratch pad block until it can be more efficiently stored elsewhere. This may be when some other data is received. Unrelated data may be stored in the same page of a scratch pad block.

Abstract: Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately destined for the update block. In a preferred embodiment, an index of the data stored in the scratch pad block as well that stored in the update block is saved in an unused portion of the scratch pad block every time the scratch pad block is written to.

Abstract: In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead.

Abstract: Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately destined for the update block. Synchronization information about the order recording of updates among the streams is saved with at least one of the streams. This will allow the most recently written version of data that may exist on multiple memory blocks to be identified. In one embodiment, the synchronization information is saved in a first block and is a write pointer that points to the next recording location in a second block. In another embodiment, the synchronization information is a time stamp.

Abstract: Integrated circuit bus integrity may be verified without specialized test equipment. In a diagnostic mode, the integrated circuit may output a series of predetermined activation patterns onto the data bus to verify integrity of the data bus. Further bus verification may be provided by an address capture mode where address bus contents are reflected onto the data bus. A microprocessor may control diagnostic mode operation.

Abstract: Alignment of clusters to pages is provided in a non-volatile memory system that receives data from a host in clusters and writes data to a memory array in units of a page. Alignment is implemented within each block using offsets in logical-to-physical mapping of data. Different blocks may have different offsets. When a host sends data with different cluster boundary locations, the data may be written with different offsets so that data maintains alignment.

Abstract: A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated in a manner to level out the wear of the individual blocks through repetitive erasing and re-programming. This may be accomplished without use of counts of the number of times the individual blocks experience erase and re-programming but such counts can optionally aid in carrying out the wear leveling process. Individual active physical blocks are chosen to be exchanged with those of an erased block pool in a predefined order.

Abstract: A method and system for emulating an Fibre Channel link over a SONET transport path by which Fibre Channel data is transported across the SONET/SDH transport path. To provide link integrity, techniques to handle link failures from a Fibre Channel element to its associated Fibre Channel port, or of the SONET/SDH network linking Fibre Channel ports include transmitting error condition codes over the SONET/SDH transport path overhead to a remote Fibre Channel transport interface so that the Fibre Channel link from the remote Fibre Channel transport interface to the associated remote Fibre Channel port is disabled. Timing the length of failures and return of operation of the failed links is used to handle transient conditions and to avoid link bouncing.

Abstract: An Internet client is provided with a SOCKS server. The client comprises a processor having an operating system, and a suite of one or more Internet tools. The SOCKS proxy server includes means for intercepting and servicing connection requests from the Internet tools. Preferably, the proxy server has a predetermined Internet Protocol address, preferably the loopback address. If the loopback address is not available on the protocol stack, a redirecting mechanism is used to redirect connection requests associated with stale IP addresses to a current IP address. The SOCKS server includes a filtering mechanism for filtering connection requests to particular servers, and a monitoring mechanism for monitoring network IP activity.

Abstract: A method of downloading a file from a Internet server to an Internet client, preferably without action by the Internet client. The method begins by associating the file into a set of components at the server. A profile of the file is then generated. This profile includes identifying information for the file as well as for each component thereof. Such information preferably includes an identifier, a size value, and a code uniquely identifying the component. The file is transferred by initiating a download sequence by which each component is transferred, one-by-one, from the server to the client using an Internet protocol. When the download sequence is complete, the individual components are reassembled into the file using the profile without action by the Internet client. If the transmission is interrupted for any reason, the download sequence is restarted with the component affected by the interruption. This avoids the need to retransfer the entire file.

Abstract: A method of mapping screen display objects located by spatial coordinates into a Hypertext Markup Language (HTML) table. The spatial coordinates for each screen display object are determined, and an HTML table having rows and columns is created, wherein row heights and column widths are determined by the spatial coordinates. The screen display objects are then loaded into cells of the HTML table for display, as determined by computation based on the spatial coordinates.

Abstract: The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.

Abstract: A non-volatile memory system is organized in physical groups of physical memory locations. Each physical group (metablock) is erasable as a unit and can be used to store a logical group of data. A memory management system allows for update of a logical group of data by allocating a metablock dedicated to recording the update data of the logical group. The update metablock records update data in the order received and has no restriction on whether the recording is in the correct logical order as originally stored (sequential) or not (chaotic). Eventually the update metablock is closed to further recording. One of several processes will take place, but will ultimately end up with a fully filled metablock in the correct order which replaces the original metablock. In the chaotic case, directory data is maintained in the non-volatile memory in a manner that is conducive to frequent updates. The system supports multiple logical groups being updated concurrently.

Abstract: In a nonvolatile memory with block management system that supports update blocks with non-sequential logical units, an index of the logical units in a non-sequential update block is buffered in RAM and stored periodically into the non-volatile memory. In one embodiment, the index is stored in a block dedicated for storing indices. In another embodiment, the index is stored in the update block itself. In yet another embodiment, the index is stored in the header of each logical unit. In another aspect, the logical units written after the last index update but before the next have their indexing information stored in the header of each logical unit. In this way, after a power outage, the location of recently written logical units can be determined without having to perform a scanning during initialization. In yet another aspect, a block is managed as partially sequential and partially non-sequential, directed to more than one logical subgroup.

Abstract: A non-volatile memory is constituted from a set of memory planes, each having its own set of read/write circuits so that the memory planes can operate in parallel. The memory is further organized into erasable blocks, each for storing a logical group of logical units of data. In updating a logical unit, all versions of a logical unit are maintained in the same plane as the original. Preferably, all versions of a logical unit are aligned within a plane so that they are all serviced by the same set of sensing circuits. In a subsequent garbage collection operation, the latest version of the logical unit need not be retrieved from a different plane or a different set of sensing circuits, otherwise resulting in reduced performance. In one embodiment, any gaps left after alignment are padded by copying latest versions of logical units in sequential order thereto.

Abstract: A system and method for automatically determining a seed vigor index for a lot of seeds by analysis of a scanned image of a plurality of seedlings grown from lot of seeds, including automatically separating and analyzing overlapped seedlings. According to one aspect of the current invention, seedling analysis software is used to analyze an image of seedlings. The seedling analysis software preferably analyzes both hypocotyl and radicle lengths and thus determines the separation point between the two for each seedling. The seedling analysis software also preferably separates overlapped seedlings, preferably using a simulated annealing technique. According to another aspect of the present invention, a low-cost scanner placed in an inverted configuration in a scanner enclosure is used to generate high-quality, reproducible images of seedlings. According to yet another aspect of the present invention, a method of using ordinary germination boxes, i.e.

Abstract: A particulate omega-3 polyunsaturated fatty acid composition suitable for use as a medicament or foodstuff additive is obtained by acid precipitation from a basic dispersion or solution comprising an omega-3 polyunsaturated fatty acid, salt or ester, metabolite or other pharmacologically acceptable derivative thereof and a polymeric pharmaceutical excipient which may be a polymethacrylate or a polysaccharide or ether, ester or other derivative thereof.

Abstract: The combination of a frame, a closure element, and a closure element holding assembly. The closure element is mounted to the frame for movement between first and second positions. The closure element holding assembly has a linkage with first and second connecting ends and at least first and second link elements. The first connecting end is connected to the closure element. The second connecting end is connected to the frame. The first and second link elements are joined to each other for pivoting movement about a first axis and in such a manner that the first and second link elements can be connected to and disconnected from each other by relatively repositioning at least a part of the first link element and second link element through relative movement of the at least part of the first link element and second link element in a direction generally parallel to the first axis. In one form, one of the link elements has a post and the other link element has a socket to receive the post.