Abstract: An electronic device can include a semiconductor material including a channel region configured to conduct a current, a source contact electrically coupled to the channel region at a first location, a drain contact electrically coupled to the channel region at a second location spaced apart from the first location, a partial-polarization material on the semiconductor material between the source contact and the drain contact opposite the channel region and a gate contact on the partial-polarization material opposite the channel region and ohmically coupled to the drain contact or ohmically coupled to the source contact.

Abstract: An electronic device can include a semiconductor material including a channel region configured to conduct a current, a source contact electrically coupled to the channel region at a first location, a drain contact electrically coupled to the channel region at a second location spaced apart from the first location, a partial-polarization material on the semiconductor material between the source contact and the drain contact opposite the channel region and a gate contact on the partial-polarization material opposite the channel region and ohmically coupled to the drain contact or ohmically coupled to the source contact.

Abstract: A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Abstract: A low voltage tunnel field effect transistor includes a p-n tunnel junction, a gate-dielectric, a gate, a source-contact, and a drain-contact. The p-n tunnel junction includes a depletion region interfacing together a source-layer and a drain-layer. The depletion region includes a source-tunneling-region of the source-layer and a drain-tunneling-region of the drain-layer. When no external electric field is imposed, the depletion region of the p-n tunnel junction has an internal electric field that substantially points towards the source-tunneling-region and the drain-tunneling-region. The gate-dielectric is interfaced directly onto the drain-tunneling-region such that the drain-tunneling-region is between the source-tunneling-region and the gate-dielectric. The gate is interfaced onto the gate-dielectric such that the gate is configured to impose an external electric field which is oriented substantially in parallel to the internal electric field of the depletion region.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

Abstract: A method of fabricating a quantum well device is presented which includes forming one or more quantum wells 48 by forming an epitaxy mask followed by selective deposition of one or more epitaxial layers. Selective deposition is accomplished by forming an epitaxy mask by sidewall defined masking, followed by epitaxial deposition of one or more layers (e.g. barrier layers 40 and 44 and a quantum layer 42) The epitaxy mask is formed by patterning an e-beam resist layer (e.g. polymethylmethacrylate 36), conformally depositing a glass layer (e.g. SiO.sub.2 38) on the resist, anisotropically etching the SiO.sub.2, and then removing the e-beam resist layer. The epitaxy mask fabrication technique allows patterning to define geometries that are much smaller than the beam itself and thereby provides the means required to define nanometer dimensioned horizontal (lateral) structures on and within epitaxial layers.

Abstract: A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have openings (430) of size smaller than the electron wave packet spread to insure crystal alignment through the diode without affecting the tunneling barrier height.

Abstract: A solid-state frequency multiplier circuit (10) is provided which includes a bipolar quantum-well resonant tunneling transistor (12), a resistive load (14), and an A.C. output coupling capacitor (16), all which may be formed in a single integrated circuit or as discrete components. The value of the resistive load (14) determines the frequency multiplication factor of the circuit (10), and can produce frequencies in a range from about 2 GHz to over 20 GHz. A different embodiment of the present invention provides a frequency multiplication circuit (20) which generates a sinusoidal output waveform, without using an output A.C. coupling capacitor.

Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.

Abstract: A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have openings (430) of size smaller than the electron wave packet spread to insure crystal alignment through the diode without affecting the tunneling barrier height, and the openings (430) have an irregular (nonperiodic) shape.

Abstract: A multi-function resonant tunneling logic gate is provided in which a resonant tunneling transistor (12) includes a first terminal, a second terminal, and a third terminal. A plurality of signal inputs are coupled to the first terminal of the resonant tunneling transistor (12) through a summer (10). Furthermore, a biasing input is operable to apply a bias to the first terminal of resonant tunneling transistor (12) such that the transfer characteristic of the resonant tunneling transistor (12) can be shifted relative to the signal inputs.

Abstract: This is a method of generating noise comprising the step of switching a plurality of resonant tunneling diodes each located in the emitter or base of a multi finger transistor such that each of the resonant tunneling diodes switches at a different input voltage. Other devices and methods are also disclosed.

Abstract: This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substrate 10, a buffer layer 12 over the substrate 10, and a channel layer 14 over the buffer layer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

Abstract: This is a vertical field-effect resonant tunneling transistor device comprising: a semi-conducting substrate 46; a drain region 48 above the semi-conducting substrate; a multiple-barrier multi-well resonant tunneling diode 52, 54, 56, 58, 60 above the drain layer; a two dimensional electron gas heterostructure 64 above the multiple-barrier multi-well resonant tunneling diode; a source region 72 extending through the two dimensional electron gas and above the multiple-barrier multi-well resonant tunneling diode; ohmic contacts 70 on the source region, wherein the source region provides an ohmic connection to the two dimensional electron gas; and gate s! 68, 74 besides the source region.

Abstract: A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have characteristics of implanted oxygen segregated into oxide layers.

Abstract: This invention describes a multi-deposition system, whereby directing elemental or molecular source fluxes across a substrate in an asymmetrical manner and rotating the substrate at low rotation speeds, a superlattice is formed having a composition of A(x-.DELTA.x)B(1-(x-.DELTA.x))/A(x+.DELTA.x)B(1-(x+.DELTA.x) where .DELTA.x is a function of the nonuniform focusing of the elemental or molecular source fluxes A and B. More specifically, superlattices 18 are formed in the ternary and quaternary In(GaAl)As alloys on InP by molecular beam epitaxy without mechanical shuttering. The superlattice 18 is formed by nonuniformly directing the group III elements 22 and 24 onto the substrate 26 and rotating the substrate 26 across the beams. Periodic ordering is produced by rotation of the substrate 26 through a nonuniform distribution of source fluxes at the rotating substrate 26. The growth rate and substrate rotation rate together determine the superlattice period.