Abstract: Provided is a process for forming metallized vias in a substrate including the steps of (I) applying to an electroconductive substrate an electrodepositable coating composition onto all exposed surfaces of the substrate to form a conformal dielectric coating; (II) ablating a surface of the dielectric coating to expose a section of the substrate; (III) applying a layer of metal to all surfaces to form metallized vias in the substrate. Also disclosed are processes for fabricating a circuit assembly which include the application of an electrodoepositable coating composition onto exposed surfaces of the substrate/core to form a conformal dielectric coating thereon. The electrodepositable coating composition includes a resinous phase dispersed in an aqueous phase, where the resinous phase has a covalently bonded halogen content of at least 1 percent by weight. The dielectric coating derived therefrom has a low dielectric constant and low dielectric loss factor.

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract: The present invention relates to a polishing pad. In particular, the polishing pad of the present invention comprises a sublayer, a middle layer, and a top layer which can function as a polishing layer. The polishing pad of the present invention is useful for polishing articles and particularly useful for chemical mechanical polishing or planarization of a microelectronic device, such as a semiconductor wafer.

Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Abstract: Provided is a process for creating a via through a substrate including the steps of (a) providing a substantially void-free film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition. Also disclosed is a process of fabricating a circuit assembly which includes building patterned circuit layers upon a substrate that has vias provided by the aformentioned process.

Abstract: The present invention relates to a polishing pad. In particular, the polishing pad of the present invention can include a window area. The window area can be formed in the pad using a cast-in-place process. The polishing pad of the present invention can be useful for polishing articles and can be especially useful for chemical mechanical polishing or planarization of a microelectronic device, such as a semiconductor wafer. The window area of the polishing pad of the present invention can be particularly useful for polishing or planarizing tools that are equipped with through-the-platen wafer metrology.

Abstract: The present invention relates to a polishing pad. In particular, the polishing pad of the present invention can include a window. The polishing pad of the present invention can be useful for polishing articles and can be especially useful for chemical mechanical polishing or planarization of a microelectronic device, such as a semiconductor wafer. The window of the polishing pad is at least partially transparent and thus, can be particularly useful with polishing or planarizing tools that are equipped with through-the-platen wafer metrology.

Abstract: The present invention relates to a polishing pad. In particular, the polishing pad of the present invention comprises a sublayer, a middle layer, and a top layer which can function as a polishing layer. The polishing pad of the present invention is useful for polishing articles and particularly useful for chemical mechanical polishing or planarization of a microelectronic device, such as a semiconductor wafer.

Abstract: The present invention relates to an electrodepositable coating composition having a resinous phase dispersed in an aqueous medium. The resinous phase includes (a) an ungelled, active hydrogen-containing, ionic salt group-containing resin; and (b) a curing agent reactive with the active hydrogens of the resin (a). The resinous phase has a covalently bonded halogen content based on total weight of resin solids present in the resinous phase such that when the composition is electrodeposited and cured, the cured film passes flame resistance testing in accordance with IPC-TM-650, and has a dielectric constant of less than or equal to 3.50. The invention also is directed to a method for forming a dielectric coating on an electroconductive substrate using the electrodepositable coating composition, as well as to a substrate coated with the electrodepositable composition.

Abstract: A pigmented curable composition adapted for decorating ceramic substrates (e.g., glass bottles) comprises curable organic binder and solid spherical particles (glass or polymer) having diameters of 10 to 50 microns for facilitating overprinting of additional layers. The preferred embodiment comprises: (a) reactive organic resin component in which epoxy groups comprise the major reactive functionality; (b) amino-functional curing agent; (c) blocked polyisocyanate; and (d) 5 to 35 percent solid spherical particles having diameters of 10 to 50 microns.

Abstract: The present invention relates to an electrodepositable coating composition having a resinous phase dispersed in an aqueous medium. The resinous phase includes (a) an ungelled, active hydrogen-containing, ionic salt group-containing resin; and (b) a curing agent reactive with the active hydrogens of the resin (a). The resinous phase has a covalently bonded halogen content based on total weight of resin solids present in the resinous phase such that when the composition is electrodeposited and cured, the cured film passes flame resistance testing in accordance with IPC-TM-650, and has a dielectric constant of less than or equal to 3.50. The invention also is directed to a method for forming a dielectric coating on an electroconductive substrate using the electrodepositable coating composition, as well as to a substrate coated with the electrodepositable composition.

Abstract: Provided is a process for creating a via through a substrate including the steps of (a) providing a substantially void-free film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition. Also disclosed is a process of fabricating a circuit assembly which includes building patterned circuit layers upon a substrate that has vias provided by the aformentioned process.

Abstract: Provided is a process for forming metallized vias in a substrate including the steps of (I) applying to an electroconductive substrate an electrodepositable coating composition onto all exposed surfaces of the substrate to form a conformal dielectric coating; (II) ablating a surface of the dielectric coating to expose a section of the substrate; (III) applying a layer of metal to all surfaces to form metallized vias in the substrate. Also disclosed are processes for fabricating a circuit assembly which include the application of an electrodoepositable coating composition onto exposed surfaces of the substrate/core to form a conformal dielectric coating thereon. The electrodepositable coating composition includes a resinous phase dispersed in an aqueous phase, where the resinous phase has a covalently bonded halogen content of at least 1 percent by weight. The dielectric coating derived therefrom has a low dielectric constant and low dielectric loss factor.

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract: A circuit board layer 2 in accordance with the present invention includes a conductive sheet 4 sandwiched between an insulating top layer 10 and an insulating bottom layer 14. The top and bottom layers 10 and 14 and the conductive sheet 4 define the circuit board layer 2 having an edge that includes an edge 20 of the conductive sheet 4. An insulating edge layer 18 covers substantially all of the edge 20 of the conductive sheet 4.

Abstract: A polishing pad is described as comprising, (a) particulate polymer which can be chosen from particulate thermoplastic polymer (e.g., particulate thermoplastic polyurethane), particulate crosslinked polymer (e.g., particulate crosslinked polyurethane and/or particulate crosslinked polyepoxide) and mixtures thereof; and (b) organic polymer binder (e.g., polyurethane binder and/or polyepoxide binder), which can bind the particulate polymer together, wherein said organic polymer binder can be prepared in-situ. The particulate polymer and organic polymer binder can be distributed substantially across the work surface the polishing pad, and the pad can have a percent pore volume of from 2 percent by volume to 50 percent by volume, based on the total volume of said polishing pad.

Abstract: Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Abstract: A polishing pad is described as comprising, (a) particulate polymer selected from particulate thermoplastic polymer (e.g., particulate thermoplastic polyurethane), particulate crosslinked polymer (e.g., particulate crosslinked polyurethane and/or particulate crosslinked polyepoxide) and mixtures thereof; and (b) crosslinked organic polymer binder (e.g., crosslinked polyurethane binder and/or crosslinked polyepoxide binder), which binds the particulate polymer together. The particulate polymer and crosslinked organic polymer binder are distributed substantially uniformly throughout the polishing pad, and the pad has a percent pore volume of from 2 percent by volume to 50 percent by volume, based on the total volume of said polishing pad. Polishing pad assemblies are also described.

Abstract: A printing medium comprising a substrate having at least one surface and a coating on the surface wherein the coating comprises: (a) binder comprising: (1) organic polymer which is substantially free of ammonium groups, (2) first cationic addition polymer consisting essentially of quaternary ammonium-containing mer units derived from addition monomer and ammonium-free mer units derived from addition monomer, and (3) second cationic addition polymer consisting essentially of secondary, tertiary, or both secondary and tertiary ammonium-containing mer units derived from addition monomer and ammonium-free mer units derived from addition monomer, wherein the binder constitutes from 20 to 90 percent by weight of the coating; and (b) finely divided substantially water-insoluble filler particles which have a maximum dimension of less than 500 nanometers, are distributed throughout the binder, and constitute from 10 to 80 percent by weight of coating.

Abstract: A method comprising heating to elevated temperature a ceramic substrate having thereon a sequence of coatings of pigmented coating compositions wherein each of said pigmented coating compositions comprises: (a) reactive organic resin which is polyhydroxy-functional, polyepoxy-functional, or both epoxy-functional and hydroxy-functional; (b) reactive wax; (c) color-imparting pigment; and (d) blocked polyisocyanate; wherein: (e) the pigmented coating composition of at least one coating of the sequence is substantially free of amino-functional curing agent; and (f) the pigmented coating composition of at least one other coating of the sequence further comprises amino-functional curing agent; to crosslink all of the pigmented coating compositions of the coatings of the sequence and to adhere the sequence to the ceramic substrate. The preferred ceramic substrates are glass bottles.