Abstract: A spread-spectrum signal generator includes four differential input signal terminals, a differential output signal terminal, four interconnected mixer control subcircuits, a 4-input differential mixer, a first current source having a magnitude which sets the mixer's 3 db bandwidth, and a second current source having a magnitude which controls a frequency difference between the differential output signal the differential input signals. In a preferred embodiment, this frequency difference and the frequency of the differential output signal are modulated through the modulation of the second current source magnitude. The frequency of the modulation is equal to the frequency of the second current source modulation, and the magnitude of the output signal frequency modulation is proportional to the magnitude of the second current source modulation.

Abstract: So as to compare an amplitude of a differential input signal to a threshold, a signal detection circuit includes first and second matched input signal level-shifters, a comparator threshold generation circuit, and a two-stage comparator. The differential input signal is comprised of a true input signal and a complement input signal, and the first input signal level-shifter is coupled to the true input signal, and the second input level-shifter is coupled to the complement input signal. The comparator threshold generation circuit is matched to the input signal level-shifters and outputs first and second compare voltages. The first stage of the two-stage comparator outputs a low signal if the more positive of the level-shifted input signals is greater than the more positive of the compare voltages.

Abstract: So as to generate multiple output signals whose phases are evenly spaced about 360 degrees, and having a frequency equal to that of an input signal, a phase multiplier circuit includes three or more instances of a phase multiplier subcircuit and additional circuitry configured in a negative feedback loop. Each phase multiplier subcircuit includes a difference circuit, a loop filter transistor, and a voltage-controlled delay circuit. The difference circuit converts to a phase current a delay from an input signal to the delay circuit to an output signal from the delay circuit, and subtracts from the phase current a bias current proportional to the smallest positive delay from the output signal with the largest phase to the output signal with the smallest phase. The subtracted current is integrated by the loop filter transistor, and steady-state operation is achieved when for each phase multiplier subcircuit, the bias current is equal to the phase current.

Abstract: A resistor mirror which biases transistors substantially in their linear region of operation and in such a way that their combined parallel resistance is equal to the resistance of a reference resistor. The resistor mirror may include three or more offset control circuits, a feedback control circuit with a reference resistor, a reference voltage-controlled resistor, and one or more additional voltage-controlled resistors. The offset control circuit includes two voltage-controlled current sources. Three or more offset control circuits are connected in a manner so as to affect an equal number of resistor control output terminals coupled to the reference voltage-controlled resistor and to the additional voltage-controlled resistors. To minimize signal coupling between multiple voltage-controlled resistors coupled to the same resistor control output terminals, and to insure stability in the circuit's operating point, a filter capacitor is coupled to each resistor control output terminal.

Abstract: A mixer system includes a multi-phase signal generator, a mixer, and a mixer control circuit. The multi-phase signal generator generates a plurality of mixer input signals, where each has a frequency equal to the others, and a phase, and where the phases are distributed between 0 to 360 degrees. The mixer control circuit generates a plurality of mixer control voltages which are controlled by digital state control input signals. Each mixer control voltage controls the influence of a corresponding mixer input signal on the mixer output signal. In a preferred embodiment, the mixer control voltage is generated by storing a charge on a capacitor, and said charge is increased or decreased through the combined action of the digital state control input signals and the mixer control voltages by means of interconnected mixer control subcircuits.

Abstract: A resistor mirror which biases transistors substantially in their linear region of operation and in such a way that their combined parallel resistance is equal to the resistance of a reference resistor. The resistor mirror may include three or more offset control circuits, a feedback control circuit with a reference resistor, a reference voltage-controlled resistor, and one or more additional voltage-controlled resistors. The offset control circuit includes two voltage-controlled current sources. Three or more offset control circuits are connected in a manner so as to affect an equal number of resistor control output terminals coupled to the reference voltage-controlled resistor and to the additional voltage-controlled resistors. To minimize signal coupling between multiple voltage-controlled resistors coupled to the same resistor control output terminals, and to insure stability in the circuit's operating point, a filter capacitor is coupled to each resistor control output terminal.

Abstract: A high-speed differential sampling flip-flop includes a differential data input, a differential offset control input, a sampling clock input, an output, a sampling latch, and an RS latch. The sampling latch includes a sampling latch reset circuit, a current steering circuit, first and second switches, and a regenerative latch. The sampling latch reset circuit is coupled to a first power supply and the current steering circuit. The current steering circuit has first and second control terminals which are coupled to the differential data input. The first switch is coupled between the current steering circuit and a second power supply. The regenerative latch is coupled to the current steering circuit, the second switch, and a third power supply. The sampling latch also includes first and second offset control current sources coupled to the current steering circuit and the second power supply, and having first and second control terminals coupled to the differential offset control input.

Abstract: A latching comparator includes first and second current integration nodes having first and second integration capacitances, respectively. A current source applies a first tail current to a current steering circuit which steers the tail current onto the first and second current integration nodes as a function of first and second data signals. An offset adjustment circuit is coupled to the first current integration node for adjusting the first integration capacitance relative to the second integration capacitance. A latch circuit is coupled to the first and second current integration nodes and has a data output.

Abstract: A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.

Abstract: A differential-to-CMOS level converter includes a differential-to-CMOS conversion circuit, first and second buffers and a cross-over adjustment circuit. The conversion circuit has first and second differential input terminals and first and second complementary output terminals. The first buffer has a buffer input coupled to the first complementary output and has a buffer output. The second buffer has a buffer input coupled to the second complementary output and has a buffer output. The cross-over adjustment circuit has first and second voltage measurement inputs coupled to the first and second buffer outputs and has first and second offset current outputs coupled to the first and second buffer inputs, respectively.

Abstract: An n:1 time division multiplexer includes a multiphase clock generator, a data multiplexer, a reference multiplexer, a reference generator and a comparison circuit. The multiphase clock generator has a plurality of select clock outputs with different phases. The data multiplexer has a plurality of data inputs, a plurality of select clock inputs and a data output. The select clock inputs of the data multiplexer are coupled to corresponding select clock outputs. The reference multiplexer has a plurality of reference data inputs, a plurality of select clock inputs and a first reference output. The select clock inputs of the reference multiplexer are coupled to corresponding select clock outputs. The reference generator has a second reference output. The comparison circuit has first and second comparison inputs coupled to the first and second reference outputs, respectively, and has a comparison output coupled to the plurality of select clock outputs.

Abstract: A voltage-controlled oscillator includes at least one voltage-controlled delay element and a reference voltage generator. The voltage-controlled delay element has first and second voltage supply inputs, a control voltage input, a signal input and a signal output. The reference voltage generator has a voltage input coupled to the control voltage input and a voltage output coupled to the first voltage supply input.

Abstract: A digital-to-analog converter (DAC) for converting a multi-bit digital word into a corresponding analog value. The converter divides the digital word into a least significant word portion n.sub.1 and a most significant word portion n.sub.2. The portions overlap in that the weight of the most significant bit (msb) of word portion n.sub.1 is the same as the weight of the least significant bit (lsb) of word portion n.sub.2. The converter detects when the lsb of word portion n.sub.2 changes state, and responsively inverts the state of the msb of word portion n.sub.1. Word portions n.sub.1 and n.sub.2 are then translated into respective analog values which are summed together.

Abstract: A current reference circuit includes a first, current mirror transistor having a gate coupled to a first feedback node, a source coupled to a first supply terminal and a drain forming a first reference node. A second, current mirror transistor has a gate coupled to the first feedback node, a source coupled to the first supply terminal and a drain forming a second reference node. A third transistor has a gate coupled to a second feedback node, a source coupled to a second supply terminal and a drain coupled to the first reference node. A fourth transistor has a gate coupled to the second feedback node, a source coupled to the second supply terminal and a drain coupled to the second reference node. A first operational amplifier has a first input coupled to the first reference node, a second input coupled to a bias node and an output forming the first feedback node.

Abstract: A self-timed phase detector for detecting the phase of an input signal, such as a high speed serial data stream. The self-timed phase detector includes a precharged latch, a phase detector circuit and a data valid gate. The precharged latch has a latch input, a sample clock input and first and second complementary latch outputs. The first and second complementary latch outputs have an active state and a precharged state. The phase detector circuit is coupled to the first latch output and generates a phase signal on a phase output as a function of the phase of the input signal. The data valid gate is coupled to the phase output for passing the phase signal when the latch outputs are in the active state and for blocking the phase signal when the latch outputs are in the precharged state.

Abstract: A phase-locked loop includes a phase/frequency detector, a charge pump, a voltage-controlled oscillator and a frequency divider coupled together to form a feedback loop, the feedback loop having a filter node between the charge pump and the voltage-controlled oscillator for coupling to an off-chip loop filter. A first electrostatic discharge (ESD) protection device is coupled to the filter node, which has leakage path through which a leakage current flows. A filter leakage cancellation circuit is coupled to the filter node and includes a second ESD protection device which generates a reference current that is equal to the leakage current. The filter leakage cancellation circuit applies the reference current to the filter node such that the reference current is opposite to and cancels the leakage current.

Abstract: A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.