Patents by Inventor Alan J. Drake

Alan J. Drake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10156882
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 10152107
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: December 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 9767917
    Abstract: An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional control over the SRAM device, particularly during a write operation. In one embodiment, a system of SRAM memory devices is configured as a smart sensor with real-time corrective circuit action. The system and method samples write and read timing operations and is adaptable by performing real-time corrective action. The degrading of PFET voltage to reduce it strength and improve write characteristics include an implementation that includes a charge pump controllable for altering by decreasing a voltage applied to the PFET of a selected memory cell. In a further embodiment, an edge detector is built into the circuit that real-time assesses the strength of the memory write operation. In a further implementation, control logic functions as a Finite State Machine.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: September 19, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alan J. Drake, Rajiv V. Joshi
  • Publication number: 20170103817
    Abstract: An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional control over the SRAM device, particularly during a write operation. In one embodiment, a system of SRAM memory devices is configured as a smart sensor with real-time corrective circuit action. The system and method samples write and read timing operations and is adaptable by performing real-time corrective action. The degrading of PFET voltage to reduce it strength and improve write characteristics include an implementation that includes a charge pump controllable for altering by decreasing a voltage applied to the PFET of a selected memory cell. In a further embodiment, an edge detector is built into the circuit that real-time assesses the strength of the memory write operation. In a further implementation, control logic functions as a Finite State Machine.
    Type: Application
    Filed: October 13, 2015
    Publication date: April 13, 2017
    Inventors: Alan J. Drake, Rajiv V. Joshi
  • Publication number: 20170102732
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 13, 2017
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Publication number: 20170102761
    Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 13, 2017
    Inventors: Francesco A. Campisano, Alan J. Drake, Michael S. Floyd, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 9612612
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Patent number: 9571100
    Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, David W. Shan, Mrigank Sharad
  • Patent number: 9477568
    Abstract: A mechanism is provided for determining a modeled age of a set of interconnect groups in a set of cores in a set of multi-core processors. For each interconnect group in the set of interconnect groups in the set of cores on the set of multi-core processors, a determination is made of a current modeled age of the interconnect group. A determination is then made as to whether at least one current modeled age of the interconnect group for the set of interconnect groups is greater than an end-of-life value. Responsive to at least one current modeled age of the interconnect group being greater than the end-of-life value, an indication to take corrective action with the at least one associated interconnect group is sent.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Jon A. Casey, Sungjun Chun, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani, Jeonghee Shin, Thomas A. Wassick, Victor Zyuban
  • Patent number: 9465373
    Abstract: A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: October 11, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan J. Drake, Michael S. Floyd, Tilman Gloekler, Charles R. Lefurgy, Karthick Rajamani
  • Patent number: 9459599
    Abstract: A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan J. Drake, Michael S. Floyd, Tilman Gloekler, Charles R. Lefurgy, Karthick Rajamani
  • Patent number: 9407247
    Abstract: A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan J. Drake, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Publication number: 20160105177
    Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Application
    Filed: December 17, 2015
    Publication date: April 14, 2016
    Inventors: ADITYA BANSAL, THOMAS J. BUCELOT, ALAN J. DRAKE, PHILLIP J. RESTLE, DAVID W. SHAN, MRIGANK SHARAD
  • Patent number: 9310424
    Abstract: A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Ronald J. Bolam, Alan J. Drake, Charles R. Lefurgy, Barry P. Linder, Steven W. Mittl, Karthick Rajamani
  • Patent number: 9298250
    Abstract: A circuit for monitoring and controlling a clock signal generated by a clock source in a microprocessor device may include a voltage divider network that provides a plurality of voltages, a selector device that receives the plurality of voltages and provides a scaled supply voltage and a scaled ground voltage from the plurality of voltages, and at least one delay element that receives the scaled supply voltage and the scaled ground voltage and generates a delayed pulse signal by applying a delay to each pulse of the clock signal. The delayed pulse signal may include a delay magnitude that is controllable by the scaled supply voltage and the scaled ground voltage, such that the delayed pulse signal is used to generate a frequency correction signal based on a variation to a supply voltage of the microprocessor. The frequency correction signal may then be applied to the clock source.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Alan J. Drake, David T. Hui, Pawel Owczarczyk, Marshall D. Tiner, Xiaobin Yuan
  • Patent number: 9276563
    Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, David W. Shan, Mrigank Sharad
  • Publication number: 20150365076
    Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: ADITYA BANSAL, THOMAS J. BUCELOT, ALAN J. DRAKE, PHILLIP J. RESTLE, DAVID W. SHAN, MRIGANK SHARAD
  • Patent number: 9117011
    Abstract: Guardband validation for a device having a critical path monitor involves first applying multiple calibration settings to the monitor during functional operation of the processor, and recording corresponding guardbands which result in reduced timing margin. A desired guardband can later be selected for validation. The calibration settings can be based on delays for a critical path. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert W. Berry, Jr., Alan J. Drake, Michael S. Floyd, Richard L. Willaman
  • Publication number: 20150234422
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 20, 2015
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G.R. Thomson
  • Patent number: 9111933
    Abstract: A distributed active transformer is provided comprising a primary and a secondary winding. The primary winding comprises a first set of conductive vias extending in a direction between a first surface and a second surface of an element, a first set of first electrically conductive lines extending along the first surface, and a first set of second electrically conductive lines extending along the second surface. The secondary winding comprises a second set of conductive vias extending in a direction between the first surface and the second surface, a second set of first electrically conductive lines extending along the first surface, and a second set of second electrically conductive lines extending along the second surface. When energized, the primary winding generates magnetic flux extending in a direction parallel to the first surface and the second surface. The secondary winding receives energy transferred by the magnetic flux generated by the primary winding.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: August 18, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gary D. Carpenter, Alan J. Drake, Rachel Gordin, Michael J. Shapiro, Edmund J. Sprogis