Abstract: A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.

Abstract: A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

Abstract: A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.

Abstract: A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.

Abstract: A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.

Abstract: A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

Abstract: A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.

Abstract: A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node.

Abstract: An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it with feedback coupled from an output of the functional logic block, when test mode operation is selected. The signal path from the de-selected input to the output is selected so that the signal path will oscillate, and a characteristic frequency or phase of the output signal is measured to determine the delay. Other inputs to the functional logic block are set to a predetermined set of logic values. The selection may be made at a register preceding the digital inputs or made in the first level of logic of the functional logic block.

Abstract: A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

Abstract: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).

Abstract: A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

Abstract: A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.

Abstract: A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.

Abstract: A circuit for dynamically monitoring the operation of an integrated circuit under differing temperature, frequency, and voltage (including localized noise and droop), and for detecting early life wear-out mechanisms (e.g., NBTI, hot electrons).

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.