Patents by Inventor Alan J. Magnus

Alan J. Magnus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8138062
    Abstract: A method for electrically coupling a first wafer with a second wafer is provided. The method includes bonding the first wafer with the second wafer using a bonding material. The method further includes forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer. The method further includes forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: March 20, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lianjun Liu, Lisa H. Karlin, Alan J. Magnus
  • Publication number: 20110143476
    Abstract: A method for electrically coupling a first wafer with a second wafer is provided. The method includes bonding the first wafer with the second wafer using a bonding material. The method further includes forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer. The method further includes forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Inventors: LIANJUN LIU, LISA H. KARLIN, ALAN J. MAGNUS
  • Patent number: 7892950
    Abstract: A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: February 22, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alan J. Magnus, Justin E. Poarch, Jason R. Wright
  • Publication number: 20100279467
    Abstract: A method (20, 104) for processing a panel (26, 128) during semiconductor device (52) fabrication entails forming grooves (72, 142) in a surface (34, 132) of the panel (26, 128) coincident with a dicing pattern (54) for the panel (26, 128). The grooves (72, 142) extend partially through the panel (26, 128) so that the panel (26, 128) remains intact. The grooves (72, 142) relieve stress in the panel (26, 128) to reduce panel (26, 128) warpage, thus enabling the panel (26, 128) to be reliably held on a support structure (88, 98, 138) via vacuum when undergoing further processing, such as solder printing (86). The method (20, 104) further entails, dicing (96, 152) through the panel (26, 128) from the surface (34, 132) in accordance with the dicing pattern (54) while the panel (26, 128) is mounted on the support structure (98, 138) to singularize the semiconductor devices (52).
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Alan J. Magnus, Justin E. Poarch, Jason R. Wright
  • Patent number: 7132303
    Abstract: One embodiment relates to using a robust metal layer of a semiconductor device to form landing pads. In one embodiment, a sputterable, nonwettable refractory metal is used as a solder mask for the landing pads. A second device may then be coupled to the robust metal layer landing pads of the semiconductor device. In one embodiment, the landing pads are formed while the semiconductor device is in wafer form, and a second device is then coupled to the landing pads of each of the plurality of semiconductor devices within the wafer, such that each semiconductor device within the wafer is electrically coupled to a second device. In this manner, each semiconductor device within the wafer and its corresponding second device may be probed and tested as a system. After probing and testing, the wafer may be singulated into a plurality of individual device assemblies which may then be packaged.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: November 7, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James J. Wang, Alan J. Magnus, Justin E. Poarch
  • Patent number: 6248664
    Abstract: A dielectric layer (27) is formed between a semiconductor surface (24) and an electrical contact (26) to promote adhesion of the contact (26). The dielectric layer (27) is formed by cleaning operation followed by a chemical oxidation.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: June 19, 2001
    Assignee: Semiconductor Components Industries LLC
    Inventors: Naresh C. Saha, Alan J. Magnus