Abstract: A ferroelectric device includes a semiconductor channel region, a gate electrode, and a ferroelectric gate dielectric located between the channel region and the gate electrode, and including a plurality of ferroelectric gate dielectric portions having different structural defect densities.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A magnetoresistive memory device includes a magnetic-exchange-coupled layer stack containing a free layer, a reference layer and an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the reference layer, and an insulating spacer layer located in a series connection with the magnetic-exchange-coupled layer stack between a first electrode and a second electrode. The first electrode and the second electrode are configured to provide a programming voltage across the magnetic-exchange-coupled layer stack and the insulating spacer layer.

Abstract: A magnetoresistive memory device includes a magnetic tunnel junction comprising a free layer, a reference layer, and an insulating tunnel barrier layer located between the free layer and the reference layer, a perpendicular magnetic anisotropy (PMA) ferromagnetic layer that is vertically spaced from the free layer, an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the PMA ferromagnetic layer. The magnetoresistive memory device is a hybrid magnetoresistive memory device which is programmed by a combination of a spin-torque transfer effect and a voltage-controlled exchange coupling effect.

Abstract: A magnetoresistive memory device includes a magnetic-exchange-coupled layer stack containing a free layer, a reference layer and an electrically conductive, non-magnetic interlayer exchange coupling layer located between the free layer and the reference layer, and an insulating spacer layer located in a series connection with the magnetic-exchange-coupled layer stack between a first electrode and a second electrode. The first electrode and the second electrode are configured to provide a programming voltage across the magnetic-exchange-coupled layer stack and the insulating spacer layer.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

Abstract: A ferroelectric device includes a semiconductor channel region, a gate electrode, and a ferroelectric gate dielectric located between the channel region and the gate electrode, and including a plurality of ferroelectric gate dielectric portions having different structural defect densities.

Abstract: A ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and at least one of a thickness of 1 to 5 monolayers of atoms of the semiconductor material or includes a two-dimensional charge carrier gas layer, a source contact contacting a first portion of the two-dimensional semiconductor material layer, a drain contact contacting a second portion of the two-dimensional semiconductor material layer, a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer, and a conductive gate electrode located adjacent to the ferroelectric memory element.

Abstract: A recording medium having improved signal-to-noise ratio (SNR) capabilities includes dual cap layers over the recording layer, where the Curie temperature of the first cap layer over the recording layer is greater than the Curie temperature of the recording layer, and the Curie temperature of the second cap layer over the first cap layer is greater than the Curie temperature of the first cap layer. The first cap layer may be composed of a magnetically hard material, such as L10 CoPt, where the second cap layer may be composed of a magnetically soft material, such as Co. Such a medium is particularly useful in the context of heat-assisted magnetic recording (HAMR).

Abstract: The present invention relates to magnetic random access memory (MRAM) storage devices based on multiferroic tunnel junctions in which ferroelectric polarization is used to control and manipulate the memory state. Invention methods include: (1) method of producing tunneling electroresistance (TER) effect in multiferroic tunnel junction (MFTJ) at finite bias; (2) method of controlling the TER effect in an MFTJ at infinite bias via the switching of the relative orientation of the ferromagnetic leads; (3) method of producing monotonous bias dependence of the tunneling magnetoresistance (TMR) in a MFTJ; (4) method of controlling the size and direction of the parallel spin transfer torque (STT) component and the perpendicular STT component across the MFTJ; (5) method of producing a monotonous bias dependence of the perpendicular STT component across an MFTJ; and (6) method of controlling the size and sign of the interlayer exchange coupling in an MFTJ.

Abstract: The present invention relates to magnetic random access memory (MRAM) storage devices based on multiferroic tunnel junctions in which ferroelectric polarization is used to control and manipulate the memory state. Invention methods include: (1) method of producing tunneling electroresistance (TER) effect in multiferroic tunnel junction (MFTJ) at finite bias; (2) method of controlling the TER effect in an MFTJ at infinite bias via the switching of the relative orientation of the ferromagnetic leads; (3) method of producing monotonous bias dependence of the tunneling magnetoresistance (TMR) in a MFTJ; (4) method of controlling the size and direction of the parallel spin transfer torque (STT) component and the perpendicular STT component across the MFTJ; (5) method of producing a monotonous bias dependence of the perpendicular STT component across an MFTJ; and (6) method of controlling the size and sign of the interlayer exchange coupling in an MFTJ.