Abstract: An apparatus and a method for photoreducing copper oxide layers from semiconductor wafers during the processes of forming interconnects in advanced IC manufacturing. The apparatus comprises a reaction chamber with a high intensity UV light source and a wafer holder in the chamber. The UV light source is made of arrays of microdischarge devices fabricated on a semiconductor wafer where each of the microdischarge devices has the structure of a hollow cathode. Multiple arrays of microdischarge devices can be assembled together to make a planar UV lamp so as to provide a sufficient area for the UV illumination. The wafer holder in the chamber is made rotatable for a better uniformity during the photoreduction process. A non-oxidizing gas is flowed into the chamber to prevent instant and subsequent oxidation on the copper surface.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location.

Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual memory cells is ideally equal less than 8F2, where “F” is no greater than 0.

Abstract: A microelectronic device fabricating method includes providing a substrate having a beveled portion and forming a layer of structural material on the beveled portion. Some of the structural material can be removed from the beveled portion by anisotropic etching to form a device feature from the structural material. The device feature can be formed on the beveled portion as with a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Structural material can be removed from the beveled portion to form an edge defined feature on a substantially perpendicular edge of the substrate. The beveled portion and perpendicular edge can be part of a mandril. The mandril can be removed from the substrate after forming the edge defined feature.

Abstract: A metal oxide layer may made more highly oxidized by exposing the layer to sulfur trioxide. The leakage current of the layer may thereby be decreased, providing a capacitor containing such a layer with improved performance properties. The capacitor may be incorporated into a dynamic random access memory cell or other structure useful in the semiconductor or other industry.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: A metal oxide layer may made more highly oxidized by exposing the layer to sulfur trioxide. The leakage current of the layer may thereby be decreased, providing a capacitor containing such a layer with improved performance properties. The capacitor may be incorporated into a dynamic random access memory cell or other structure useful in the semiconductor or other industry.

Abstract: An intermediate construction of an integrated circuit includes a semiconductive substrate and a raised mandril over the substrate. The raised mandril may be raised out from the substrate and have at least one edge substantially perpendicular to the substrate and at least one beveled edge. A layer of structural material may form an edge defined feature on the at least one perpendicular edge.

Abstract: Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an opening into an interior volume. At least a portion of the rim is capped by forming a material which is different from the capacitor storage node layer over the rim portion. After the rim is capped, a capacitor dielectric region and a cell electrode layer are formed over the storage node layer.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred-implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells. Adjacent memory cells are isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual memory cells is less than 8F2, where “F” is no greater than 0.25 micron.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: An electrical and thermal contact which includes an intermediate conductive layer, an insulator component, and a contact layer. The insulator component is fabricated from a thermally insulative material and may be sandwiched between the intermediate conductive layer and the contact layer. The electrical and thermal contact may be fabricated by forming a first conductive layer on a surface of the semiconductor device, depositing a dielectric layer adjacent the first layer, patterning the dielectric layer to define the insulator component, and forming a second conductive layer adjacent the insulator component and in partial contact with the first layer. The first and second layers are respectively patterned to define the intermediate conductive layer and the contact layer. The electrical and thermal contact effectively contains heat within and prevents heat from dissipating from a contacted structure, such as a phase change component that may be switched between two or more electrical states.

Abstract: A metal oxide layer may made more highly oxidized by exposing the layer to sulfur trioxide. The leakage current of the layer may thereby be decreased, providing a capacitor containing such a layer with improved performance properties. The capacitor may be incorporated into a dynamic random access memory cell or other structure useful in the semiconductor or other industry.