Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: An electrical and thermal contact which includes an intermediate conductive layer, an insulator component, and a contact layer. The insulator component is fabricated from a thermally insulative material and may be sandwiched between the intermediate conductive layer and the contact layer. The electrical and thermal contact may be fabricated by forming a first conductive layer on a surface of the semiconductor device, depositing a dielectric layer adjacent the first layer, patterning the dielectric layer to define the insulator component, and forming a second conductive layer adjacent the insulator component and in partial contact with the first layer. The first and second layers are respectively patterned to define the intermediate conductive layer and the contact layer. The electrical and thermal contact effectively contains heat within and prevents heat from dissipating from a contacted structure, such as a phase change component that may be switched between two or more electrical states.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location. According to a preferred aspect of the invention, a plurality of insulated conductive lines are formed over a substrate.

Abstract: The electrical and thermal contact fabricated by forming a first layer on a surface of a semiconductor device, depositing a dielectric layer adjacent the first layer, patterning the dielectric layer to define an insulator component, and forming a second layer adjacent the insulator component and in partial contact with the first layer. The first layer contacts an adjacent structure of the semiconductor device. The first and second layers may be patterned separately or simultaneously to respectively define an intermediate conductive layer, which communicates with ths contacted structure, and a contact layer. Due to its structure, which requires relatively little electrical current to generate a desired amount of heat, the electrical and thermal contact effectively contains heat within and prevents heat from dissipating from a contacted structure, and is particularly useful for contacting and inducing a change in the electrical conductivity of structures which include phase change materials.

Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F2, where “F” is no greater than 0.

Abstract: An electrical and thermal contact which includes an intermediate conductive layer, an insulator component, and a contact layer. The insulator component is fabricated from a thermally insulative material and may be sandwiched between the intermediate conductive layer and the contact layer. The electrical and thermal contact may be fabricated by forming a first thin layer on a surface of the semiconductor device, depositing a dielectric layer adjacent the first thin layer, patterning the dielectric layer to define the insulator component, forming a second thin layer adjacent the insulator component and in partial contact with the first thin layer. The first and second thin layers are respectively patterned to define the intermediate conductive layer and the contact layer. The electrical and thermal contact effectively contains heat within and prevents heat from dissipating from a contacted structure, such as a phase change component that may be switched between two or more electrical states.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an opening i into an interior volume. At least a portion of the rim is capped by forming a material which is different from the capacitor storage node layer over the rim portion. After the rim is capped, a capacitor dielectric region and a cell electrode layer are formed over the storage node layer. In another embodiment, a capacitor storage node layer is formed within a container which is received within an insulative material. A capacitor storage node layer is formed within the container and has an outer surface. A layer of material is formed within less than the entire capacitor container and covers less than the entire capacitor storage node layer outer surface. The layer of material comprises a material which is different from the insulative material within which the capacitor container is formed.

Abstract: A method for fabricating chalcogenide memories in which ultra-small pores are formed in insulative layers using disposable spacers. The chalcogenide memory elements are positioned within the ultra-small pores. The chalcogenide memory elements thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Abstract: A microelectronic device fabricating method includes providing a substrate having a beveled portion and forming a layer of structural material on the beveled portion. Some of the structural material can be removed from the beveled portion by anisotropic etching to form a device feature from the structural material. The device feature can be formed on the beveled portion as with a pair of spaced, adjacent barrier material lines that are substantially void of residual shorting stringers extending therebetween. Structural material can be removed from the beveled portion to form an edge defined feature on a substantially perpendicular edge of the substrate. The beveled portion and perpendicular edge can be part of a mandril. The mandril can be removed from the substrate after forming the edge defined feature.

Abstract: Mechanical stress is diminished by forming an oxidation mask with silicon nitride having a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride. The silicon nitride can be graded in a substantially linear or non-linear fashion. In one embodiment, the graded silicon nitride may be formed with one type of non-linear silicon grading, an abrupt junction. In other embodiments, the silicon nitride is formed in a variety of shapes fashioned during or after silicon nitride growth. In one embodiment, the stress is reduced by forming a polysilicon buffer layer between two silicon nitride layers. In another embodiment, stress is reduced by forming the silicon nitride on a pad layer, which in turn is formed on a base layer.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A metal oxide layer may made more highly oxidized by exposing the layer to sulfur trioxide. The leakage current of the layer may thereby be decreased, providing a capacitor containing such a layer with improved performance properties. The capacitor may be incorporated into a dynamic random access memory cell or other structure useful in the semiconductor or other industry.

Abstract: Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an opening into an interior volume. At least a portion of the rim is capped by forming a material which is different from the capacitor storage node layer over the rim portion. After the rim is capped, a capacitor dielectric region and a cell electrode layer are formed over the storage node layer. In another embodiment, a capacitor storage node layer is formed within a container which is received within an insulative material. A capacitor storage node layer is formed within the container and has an outer surface. A layer of material is formed within less than the entire capacitor container and covers less than the entire capacitor storage node layer outer surface. The layer of material comprises a material which is different from the insulative material within which the capacitor container is formed.

Abstract: Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å).