Abstract: A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a plurality of match line inputs in a match line decoder, the method comprising the steps of: (a) generating a signal indicative of the location of a defective row in the array; (b) generating a set of word line select signals for selecting ones of the plurality of normal rows; (d) using the defective row signal to switch a word line select signal of the defective row to a row adjacent the defective row and switching the adjacent row word line select signals to subsequent rows upto the at least one spare row, and (e) using the defective row signal to switch the match line input of the row adjacent the defective row to the matchline input of the defective row and switching the subsequent row match line input to the adjacent row

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract: A content addressable memory (CAM) including a plurality of rows, each of the rows has a plurality of matchline segments having a plurality of CAM cells coupled thereto. A circuit is provided for precharging the matchline segments to a mismatch condition. For each segment a sense circuit detects a match and in response thereto enables a discharge path in a subsequent segment, to allow matches to be detected therein. This is propagated through all segments in a row to generate a search result for the row.

Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Abstract: A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a plurality of match line inputs in a match line decoder, the method comprising the steps of: (a) generating a signal indicative of the location of a defective row in the array; (b) generating a set of word line select signals for selecting ones of the plurality of normal rows; (d) using the defective row signal to switch a word line select signal of the defective row to a row adjacent the defective row and switching the adjacent row word line select signals to subsequent rows upto the at least one spare row, and (e) using the defective row signal to switch the match line input of the row adjacent the defective row to the matchline input of the defective row and switching the subsequent row match line input to the adjacent row

Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method comprises the following steps. A row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored. A column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored. A parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit. If the generated and stored parity bits do not match, columns of the array are cycled through. A parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated.

Abstract: The present invention relates to a process for the preparation of halo-4-phenoxyquinolines.

Abstract: A multiple CAM chip architecture for a CAM memory system is disclosed. The CAM chips are arranged in a diamond cascade configuration such that the base unit includes an input CAM chip, two parallel CAM chip networks, and an output CAM chip. The input CAM chip receives a CAM search instruction and provides the search instruction and any match address simultaneously to both CAM chip networks for parallel processing of the search instruction. Each CAM chip network provides the highest priority match address between the match address of the input CAM chip and its own match address. The output CAM chip then determines and provides the highest priority match address between the match addresses of both CAM chip networks and its own match address. Each CAM chip network can include one CAM chip, or a plurality of CAM chips arranged in the base unit diamond cascade configuration.

Abstract: A cam system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMS in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimising the number of CAMs being connected to a common forwarding bus.

Abstract: A content Addressable memory (CAM) for performing search operations using variable width search data, said CAM comprising a plurality of arrays of CAM cells, each coupled to a respective sub-search data bus, the sub-search buses being confined to form a main search data bus, to which is applied the search data; selector circuits receiving match line signals from respective CAM arrays, the match line signals being indicative of the results of a search and comparison formed in the associated CAM array, the selector circuit being responsive to a mode selection signal for selecting one or more of said match line output signals to be switched to a priority encoder and multiple match resolver (PE-MMR), wherein in a first mode the match line output signals are switched to said PE-MMR and in a second mode groups of match line output signals from selected arrays are switched to said PE-MMR.

Abstract: A priority encoder circuit for detecting multiple match in a CAM, the priority encoder comprising a plurality of inputs each for receiving a respective matchline signal, the inputs being arranged in a predetermined priority order and being enabled by a matchline signal being received thereon; a plurality of outputs corresponding to ones of said inputs; means for enabling one of the outputs corresponding to an enabled input, that is of the highest priority; and a circuit for logically combining a sufficient number of the inputs and outputs of the PE in order to determine whether more than one respective matchline signals has been received, the determination is based on an observation that for every match line input to the PE, there is a corresponding output from the PE and that the highest priority match should have the match line as well as its corresponding priority match output enabled and that if a match line output is enabled but its corresponding output is not, then there is another higher priority match

Abstract: A content addressable memory (CAM) including a plurality of rows, each of the rows comprising a plurality of matchline segments having a plurality of CAM cells coupled thereto. A circuit is provided for precharging the matchline segments to a mismatch condition. For each segment a sense circuit detects a match and in response thereto enables a discharge path in a subsequent segment, to allow matches to be detected therein. This is propagated through all segments in a row to generate a search result for the row.

Abstract: A circuit selects a highest priority signal from a plurality of input signals. The circuit comprises the following components. A plurality of serially coupled input blocks, each of which are coupled to a corresponding one of a plurality of input lines for receiving respective ones of the input signals and providing corresponding output signals. A pre-charging device coupled between a first supply voltage terminal and a first one of the serially coupled input blocks. The pre-charging device couples the supply voltage to the first one of the serially coupled input blocks in response to a clock pulse signal transition. An activation device coupled between a second supply voltage terminal and a last one of the serially coupled input blocks. The activation device couples the second supply voltage to the last one of the serially coupled input blocks in response to an activation signal transition.

Abstract: A method for reducing the coupling noise in a Content Addressable Memory (CAM), the CAM having a first bitline pair and a second bitline pair, both pairs aligned along a first axis; a first memory cell connected to the first bitline pair and a second memory cell to the second bitline pair; having a first match line and a first word line aligned along a second axis, the first match line and the first word line connecting the first and the second memory cells defining a first row in a first column; having a second row adjacent the first row, the second row comprising a third cell and a fourth cell, the third and fourth cells connecting the first and second bitline pairs and a second word line and a second match line, the method comprising arranging the first memory cell in a first orientation and the second memory cell in a second orientation, wherein the second orientation being a first axis mirror image to the first orientation; segmenting the first and second bitline pairs between the first row and the secon

Abstract: A structure for selectively programming interconnections between an input contact and an output contact segment in a multilayer semiconductor, comprising a first group of metal segments each being formed on successive layers of the semiconductor and being interconnected by vias, the first group including the output contact segment; a second group of metal segments each formed on successive layers of the semiconductor and being interconnected by vias, the second group including the input contact segment; and means for connecting a metal segment in the first group to a metal segment in a corresponding layer in the second group, thereby connecting the input contact to the output contact.

Abstract: A circuit selects a highest priority signal from a plurality of input signals. The circuit comprises the following components. A plurality of serially coupled input blocks, each of which are coupled to a corresponding one of a plurality of input lines for receiving respective ones of the input signals and providing corresponding output signals. A pre-charging device coupled between a supply voltage terminal and a first one of the serially coupled input blocks. The pre-charging device couples the supply voltage to the first one of the serially coupled input blocks in response to a clock pulse signal transition. An activation device for coupling a last one of the serially coupled input blocks to a ground voltage terminal in response to an activation signal transition. A ground voltage is propagated through the plurality of input blocks up to an input block which reflects a voltage on its input signal that is different from a pre-charge voltage state.

Abstract: A new lawn mower blade for improving the cutting edge to produce a more efficient cutting area. The inventive device includes an elongate blade member, a first scalloped cutting edge region on one end of the blade member, a second scalloped cutting edge region on the other end, a first deflecting fin on the opposite edge of the second scalloped cutting edge region, a second deflecting fin on the opposite edge of the first scalloped cutting edge region, and a mounting means for mounting the blade member to a lawnmower. The new lawn mower blade is designed to increase the surface area of the cutting edge to effectively cut grass cleaner and more even than a conventional rotary lawn mower blade.