Patents by Inventor Alan Roth
Alan Roth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130307510Abstract: In a method, a high voltage level is converted to a low voltage level by using a high side driver and a low side driver electrically coupled with the high side driver. The high side driver is substantially turned off upon a detection that the high side driver leaves a cutoff region of the high side driver during a tri-state mode.Type: ApplicationFiled: July 30, 2013Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mei-Chen CHUANG, Alan ROTH
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Publication number: 20130307663Abstract: This disclosure relates to a semiconductor device including resistor arrangement including a first resistor electrically connected to a ground voltage and a second resistor in direct physical contact with the first resistor. The second resistor is configured to receive a temperature independent current and the second resistor has thermal properties similar to those of the first resistor. This disclosure also relates to a semiconductor device including a load configured to receive an operating voltage and a voltage source configured to supply the operating voltage. The semiconductor device further includes a resistor arrangement between the load and the voltage source. This disclosure also relates to a method of using a resistor arrangement to calculate an operating current.Type: ApplicationFiled: September 14, 2012Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alan ROTH, Alexander KALNITSKY, Chien-Chung TSENG
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Patent number: 8547267Abstract: A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.Type: GrantFiled: May 29, 2012Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alan Roth, Eric Soenen, Chia Liang Tai
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Patent number: 8533522Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: September 21, 2012Date of Patent: September 10, 2013Assignee: MOSAID Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Patent number: 8519684Abstract: An integrated circuit includes a high side driver and a low side driver. The low side driver is electrically coupled with the high side driver. A circuit is electrically coupled with the high side driver and a first node between the high side driver and the low side driver. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode.Type: GrantFiled: September 8, 2010Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mei-Chen Chuang, Alan Roth
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Publication number: 20130135131Abstract: A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.Type: ApplicationFiled: May 29, 2012Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia Liang Tai, Alan ROTH, Eric SOENEN
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Publication number: 20130135782Abstract: A high accuracy on-chip thermal sensor includes an integrated circuit and sensing elements. The thermal sensor finds application in various mobile and battery powered devices and includes a processor that analyzes a measured temperature signal and decides if the thermal sensor operates in low or high power operational mode, or if the device's CPU is to be reset. A method utilizing the thermal sensor includes making comparisons to two threshold temperatures and operating at low power mode below the first threshold temperature, high power mode between the two threshold temperatures and causing reset if the second threshold temperature is exceeded. Low power operational mode includes a lower clock frequency, lower bias current and lower power consumption. Higher power operational mode is used when the upper threshold temperature is being approached and includes a higher data sampling frequency and more accurate temperature control and uses higher power.Type: ApplicationFiled: July 11, 2012Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Alan ROTH, Eric SOENEN
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Patent number: 8450990Abstract: A method of controlling a regulator includes turning on a first driver during a first cycle for a first time period. A second driver is turned on during the first cycle for a second time period. The first and second drivers are off during the first cycle for a third time period. The first time period is adjusted to become an adjusted first time period for a second cycle based on a ratio and a voltage difference between a peak value of the output voltage and a first voltage during the first cycle. The ratio refers to the first time period over the first time period and the second time period.Type: GrantFiled: August 16, 2010Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Justin Shi, Alan Roth, Justin Gaither, Eric Soenen
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Publication number: 20130119511Abstract: The present application discloses an inductor including a substrate, a first conductive line and a second conductive line formed over the substrate, a passivation layer formed over the first and the second conductive lines, and a bond wire coupling an end of the first conductive line and an end of the second conductive line. At least a portion of the at least one bond wire is positioned above an upper surface of the passivation layer. The first conductive line, the bond wire, and the second conductive line are connected to form a coil.Type: ApplicationFiled: November 10, 2011Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Justin SHI, Eric SOENEN, Alan ROTH
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Patent number: 8441235Abstract: A digital controlled battery charger comprises a power converter, a voltage sensor, a current senor, a mode selector and a digital controller. The voltage sensor and current sensor detect the voltage of a rechargeable battery and the current flowing through the rechargeable battery respectively. The mode selector selects a feedback signal from either the output of the voltage sensor or the output of the current sensor. The digital controller receives the selected feedback signal and generates a pulse width modulated signal for the power converter. Additionally, the digital controller is capable of dynamically adjusting its coefficients so that the control loop can maintain a stable system when the battery charger operates in different battery charging phases.Type: GrantFiled: February 23, 2011Date of Patent: May 14, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Justin Shi, Eric Soenen, Alan Roth
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Publication number: 20130082668Abstract: A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit.Type: ApplicationFiled: December 30, 2011Publication date: April 4, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Chung Tseng, Eric Soenen, Alan Roth, Justin Shi
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Publication number: 20130058049Abstract: A package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry. The passivation structure has at least one opening that is configured to expose at least one first electrical pad. At least one passive electrical component is disposed over the passivation structure. The at least one passive electrical component is electrically coupled with the at least one first electrical pad.Type: ApplicationFiled: August 29, 2012Publication date: March 7, 2013Applicant: TAIWAN SEMICONDUCOTR MANUFACTURING COMPANY, LTD.Inventors: Alan ROTH, Eric SOENEN, Chaohao WANG
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Publication number: 20130009795Abstract: A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Eric SOENEN, Alan ROTH, Martin KINYUA, Justin SHI, Justin GAITHER
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Patent number: 8338596Abstract: 5-Substituted-8-alkoxy[1,2,4]triazolo[1,5-c]pyrimidin-2-amines are manufactured from 2-substituted-4-amino-5-methoxypyrimidines in a process that avoids hydrazine and cyanogen halide.Type: GrantFiled: December 14, 2011Date of Patent: December 25, 2012Assignee: Dow Agrosciences LLCInventors: Craig Bott, Christopher T. Hamilton, Gary Alan Roth
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Patent number: 8324955Abstract: A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.Type: GrantFiled: March 18, 2011Date of Patent: December 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alan Roth, Ying-Chih Hsu, Justin Shi, Eric Soenen
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Patent number: 8299946Abstract: A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected.Type: GrantFiled: December 3, 2010Date of Patent: October 30, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eric Soenen, Alan Roth, Martin Kinyua, Justin Shi, Justin Gaither
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Patent number: 8296598Abstract: A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.Type: GrantFiled: May 23, 2011Date of Patent: October 23, 2012Assignee: Mosaid Technologies IncorporatedInventors: Alan Roth, Oswald Becca, Pedro Ovalle
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Publication number: 20120235728Abstract: A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.Type: ApplicationFiled: March 18, 2011Publication date: September 20, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alan Roth, Ying-Chih Hsu, Justin Shi, Eric Soenen
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Publication number: 20120194141Abstract: A digital controlled battery charger comprises a power converter, a voltage sensor, a current senor, a mode selector and a digital controller. The voltage sensor and current sensor detect the voltage of a rechargeable battery and the current flowing through the rechargeable battery respectively. The mode selector selects a feedback signal from either the output of the voltage sensor or the output of the current sensor. The digital controller receives the selected feedback signal and generates a pulse width modulated signal for the power converter. Additionally, the digital controller is capable of dynamically adjusting its coefficients so that the control loop can maintain a stable system when the battery charger operates in different battery charging phases.Type: ApplicationFiled: February 23, 2011Publication date: August 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Justin Shi, Eric Soenen, Alan Roth
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Patent number: RE43552Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.Type: GrantFiled: February 19, 2010Date of Patent: July 24, 2012Assignee: Mosaid Technologies IncorporatedInventors: Alan Roth, Sean Lord, Robert McKenzie, Dieter Haerle, Steven Smith