Abstract: A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs.

Abstract: A method and apparatus for coordinating program execution in a site controller with pattern execution in a tester executes the pattern in the tester and a pattern interruption instruction. The pattern interruption instruction causes the tester to write to a service request register in the site controller specifying a value that specifies a requested subroutine and a data source. The site controller initiates execution of the requested subroutine in the site controller using the specified data source.

Abstract: A test program generates transmit vectors (stimuli) and receive vectors (expected responses). The transmit vectors are applied to the DUT, while the receive vectors are treated as comparison values used to decide if a response from the DUT is as expected. While programming a FLASH part the test program uses TAG RAM techniques to maintain a BAD COLUMN table in one of the memory sets. This BAD COLUMN table is addressed by the same address that is applied to the DUT. If an OMIT BAD COLUMN mode is in effect, entries in this table are, by automatic action of the memory tester hardware, obtained and used to supply a replacement programming data value of all 1's that will produce an immediate and automatic indication of successful programming from the DUT. This prevents spending extra time programming a column that has been determined to be bad, without requiring an alteration in the internal mechanism of the test program.

Abstract: The problem of sequentially “squeezing” small fields of data in a larger data path in and out of a memory device can be solved in an algorithmically driven memory tester by defining sub-vectors to represent data in the small field, where a sequence of sub-vectors represents the data that would be represented by a full sized vector if such a full sized vector could be applied to the DUT. A programming construct in the programming language of the algorithmically driven memory tester allows sub-vectors to be defined, as well as an arbitrary mapping that each is to have. The arbitrary mapping is not static, but changes dynamically as different sub-vectors are encountered. Arbitrary dynamic mappings change as sub-vectors are processed, and may include the notion that, during the activity for a sub-vector, this (or these) bit(s) of a vector do not (presently) map to any pin at all of the DUT.

Abstract: An apparatus for automatically accumulating and storing information has a destination memory and an indexing circuit. The indexing circuit has an input port, a selector having a selector output, a register holding a value from the selector output and presenting the selector output value at a register output, and an accumulator accepting a value from the input port and a value from the register output and presenting a sum of the input port and register output values at an accumulator output. The selector receives the input port value from the input port, the accumulator output, and the value from the register output, the selector output being based upon a programmable selection code. The register output is connected to the destination memory .

Abstract: A waveform for an input/output signal for a device under test (DUT) is displayed. Data for the input/output signal is captured in accordance with a first data capturing mechanism. The waveform for the input/output signal is displayed using the captured data. A user is provided with an interface that allows the user to select a portion of the waveform for recapture using a second data capturing mechanism. Data for a portion of the input/output signal, corresponding to the portion of the waveform selected for recapture, is recaptured. The recapturing of data is performed using the second data capturing mechanism. The waveform for the input/output signal is redisplayed. The data recaptured using the second data capturing mechanism is used for displaying the portion of the waveform selected for recapture. The data captured in accordance with the first data capturing mechanism is used for displaying remaining portions of the waveform not selected for recapture.

Abstract: Input to a device under test (DUT) is reconstructed. For each trigger cycle of a tester in which data is to be input to the DUT stimulus, data is prepared to be placed as stimulus on pins of the DUT. Response information obtained from the DUT during a previous trigger cycle is used to construct formatting information used to adjust a value of the stimulus data. Reconstruction information sufficient to reconstruct the stimulus data is stored. The reconstruction information includes the formatting information. The reconstruction information is used to reconstruct the stimulus data placed on the pins of the device under test.

Abstract: Waveforms of input/output signals for a device under test (DUT) are simultaneously displayed. A user is presented with an interface that allows the user to specify different modes for capturing data for different input/output signals for the DUT. Data for the different input/output signals are captured in accordance with different data capturing mechanisms dependent upon the different modes specified by the user. Based on the data, waveforms for each of the different input/output signals are simultaneously displayed.

Abstract: A memory tester supports testing of multiple DUT's of the same type at a test site. The tester can be instructed to replicate the segments of the test vectors needed to test one DUT on the channels for the other DUT's. This produces patterns of transmit and receive vectors that are n-many DUT's wide. Conditional branching within the test program in response to conditions in the receive vectors (DUT failure) is supported by recognizing several types of error indications and an ability to selectively disable the testing of one or more DUT's while continuing to test the one or more that are not disabled. Also included are ways to remove or limit stimulus to particular DUT's, and ways to make all comparisons for a particular DUT appear to be “good.

Abstract: A method and apparatus for executing an integrated circuit (IC) test program including at least one calling instruction partitions at least one called subroutine into first and second subroutine portions, loads IC test program instructions into a primary memory, loads the first subroutine portion into the primary memory contiguous with the calling instruction, inserts a memory transfer access instruction after the first portion, and loads a remainder of the IC test program instructions into primary memory. The method then executes instructions from primary memory. Execution of the calling instruction in the primary memory causes the second subroutine portion to be loaded into a FIFO element from a secondary memory. The first subroutine portion executes from the primary memory. Execution of the memory transfer access instruction initiates fetching and executing the second portion of the called subroutine from a first-in-first-out (FIFO) element.

Abstract: A memory tester has a feature including a method and an apparatus, to programmably insert a latency between address and data channels. Address information is stored in a FIFO memory during a first program instruction cycle. After a desired number of program instruction cycles, the address information is retrieved during a second program instruction cycle. The retrieved address information is used to address a location in a tester memory for storage of data information received from a DUT. In this way, the data information is correlated to a latent address according to DUT specifications.

Abstract: A method for managing execution of program includes a memory management process to optimize use of primary and secondary memories 20,21, by storing all software units in the secondary memory 21 and copying specific software units necessary for execution of the program to the primary memory 20. Because the memory management process is performed during run-time, a process of calculating address values for the step of copying and offset values for the step of pattern dependency resolution are implemented in hardware. A development and debug application of the disclosed method is used to access specific memory locations without requiring a recompile and download of the code, while the data manipulator is used to perform efficient memory de-fragmentation.

Abstract: The problem is to branch back to an appropriate location within a memory tester test program, and also restore its state of algorithmic control, when an error associated therewith occurs later in time at the DUT. Owing to delays in pipelines connecting the program execution environment to the DUT and back again. These delays allow the program to arbitrarily advance beyond where the stimulus was given. The arbitrary advance makes it difficult to determine the exact circumstances that were associated with the error. A branch based on the error signal can restart a section of the test program, but it is likely only a template needing further test algorithm control information that varies dynamically as the test program executes. The solution is to equip the memory tester with History FIFO's whose depths are adjusted to account for the sum of the delays of the pipelines, relative to the location of that History FIFO.

Abstract: A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs.

Abstract: The problem is to branch back to an appropriate location within a memory tester test program, and also restore its state of algorithmic control, when an error associated therewith occurs later in time at the DUT. Owing to delays in pipelines connecting the program execution environment to the DUT and back again. These delays allow the program to arbitrarily advance beyond where the stimulus was given. The arbitrary advance makes it difficult to determine the exact circumstances that were associated with the error. A branch based on the error signal can restart a section of the test program, but it is likely only a template needing further test algorithm control information that varies dynamically as the test program executes. The solution is to equip the memory tester with History FIFO's whose depths are adjusted to account for the sum of the delays of the pipelines, relative to the location of that History FIFO.

Abstract: A trigger signal for a memory tester having algorithmic test programs detects the occurrence of a trigger specification expressed in terms of existing hardware quantities used to operate the DUT. This forms a raw hardware (breakpoint) trigger that can be further qualified according to what part of the test program is being executed. The qualified breakpoint trigger can be delayed by zero or more DUT cycles before becoming a system trigger signal that can be used to trigger a ‘scope mode and to force an error flag to a selected value so as to compel a particular path with the test program. A user interacts with a process not part of the test program to define a trigger specification from masks and comparison mechanisms that recognize the raw trigger condition at the level of the hardware register values. That process also informs the compiler as to which portions of the test program are to enable the raw trigger specification (done by setting a bit in the instruction word).

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: The present invention is directed to a method that enhances the performance of a geometry accelerator. In accordance with one aspect of the invention, the method comprises the step of receiving a color command from an application program interface (API), the color command identifying a first color for a primitive vertex. Thereafter, the invention initializes a count and receives a primitive element to draw on a screen in the first color. Then, the invention increments a count. The method further comprises the step of operating on the primitive element by a lighting machine and a plane equation machine, and repeating the steps of incrementing the count and operating on the primitive element until a specified count has been reached. Then, once the specified count has been reached, the invention operates on the primitive element without invoking either the lighting or plane equation machines., until a color command is received that specifies a second color for a primitive vertex.

Abstract: A graphics processor is disclosed having two processing units and two dual-port RAMs for passing data between the processing units. The hardware is configured to detect whether input data is primitive information or pass-through information. If it is the former, the information is processed as a primitive. If it is the latter, the hardware determines whether one of the dual-port RAMs is available. If so, the available RAM is converted into a pass-through FIFO, and the pass-through information is stored therein. An output process operates continually to send primitive results and pass-through information from the pass-through FIFO out of the graphics processor output as the information becomes available, and ensures that the correct ordering of the information is maintained. If necessary, and if both RAMs are available, both of the dual-port RAMs in the graphics processor may be used as pass-through FIFOs at the same time.