Abstract: A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface includes a plurality of geometry accelerators. A distributor divides the primitive data into chunks of primitive data and distributes the chunks to a current geometry accelerator recipient. A state controller is configured to store and resend selected primitive data to the geometry accelerators based upon whether one or more vertices of a graphics primitive are contained in more than one of the chunks of primitive data. Advantageously, this enables the computer graphics system to efficiently process primitive data while avoiding providing the geometry accelerators with an excessive amount of data than necessary for them to render the primitives.

Abstract: A system and method computes the color of a plurality of vertices of one or more graphic primitives in a graphics accelerator. The method includes the steps of receiving lighting properties of a primitive vertex and determining whether predetermined lighting properties of the vertex are the same as a previously computed vertex. If predetermined lighting properties are the same as the previously computed vertex, then the method retrieves at least one preprocessed value from a storage location; and utilizes the at least one preprocessed value to compute the vertex color. If, however, the predetermined lighting properties are not the same as the previously computed vertex, then the method computes at least one preprocessed value from the received lighting properties of the primitive vertex, stores the at least one computed preprocessed value in a storage location, and utilizes the at least one preprocessed value to compute the vertex color. The system includes at least one processing unit (e.g.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: A graphics processor is disclosed having two processing units and two dual-port RAMs for passing data between the processing units. The hardware is configured to process two graphics primitives simultaneously in a first mode, and to use both processing units simultaneously to process a single primitive in a second mode. One of the dual-port RAMs may function as a FIFO buffer in the second mode. A method for processing graphics primitives is disclosed in which one processing unit generates a set of intermediate results for a first primitive and stores them in a first RAM, and then generates a set of intermediate results for a second primitive and stores them in a second RAM while another processing unit reads the first RAM and completes calculations for the first primitive. Afterwards, the second processing unit reads the second RAM and completes calculations for the second primitive.

Abstract: A system and associated method for dynamically allocating vertex data to a plurality of geometry accelerators in a computer graphics system based upon the relative current capability of the geometry accelerators to process the data. This efficient distribution of vertex data substantially reduces the amount of time individual geometry accelerators remain idle, thereby increasing both the efficiency of each geometry accelerator as well as the overall parallel processing of vertex data. This selective utilization of geometry accelerators thereby results in a significant increase in the throughput performance of the computer graphics system. A computer graphics system in accordance with the present invention comprises a plurality of geometry accelerators and a distributor connected through two unidirectional buses that transmit data in opposite directions. The geometry accelerators are connected, through appropriate interfacing hardware, directly to an input bus.

Abstract: A system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by enabling efficient multiway logic branching functionality. Architecturally, the system is implemented as follows. A plurality of processing elements (stack) are disposed in the geometry accelerator along with a plurality of control units that are implemented in a read-only memory (ROM) via microcode. Each of the control units is configured to drive a processing element in order to modify image data. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A branch logic unit including a plurality of control unit logic elements. The plurality of control unit logic elements correspond respectively with the control units and are configured to assist with internal instruction branching within their respective control units.

Abstract: A computer graphics system for rendering graphics primitives based upon primitive data received from a host computer through a graphics interface. The primitive data may include vertex state and property state values. The computer graphics system includes a plurality of geometry accelerators configured to process the primitive data to render graphics primitives. The graphics primitives are rendered from one or more vertex states in accordance with the property states currently maintained in the rendering geometry accelerator. A distributor divides the primitive data into chunks of primitive data and distributes each of the primitive data chunks to a current geometry accelerator recipient. In one aspect of the invention, the distributor includes a state controller interposed between the host computer and said plurality of geometry accelerators.

Abstract: A method computes exponentials of a lighting equation in a geometry accelerator. In accordance with one aspect of the invention, the method includes the steps of receiving values for a first term "a" and a second term "x" of an exponential in the form a.sup.x. The method then evaluates at least one of the first and second terms to determine whether it is an integer value. If the evaluating step determines that the at least one of the terms is an integer value, then the method sets a bit in a memory location. Thereafter, the method examines a bit in the memory location. If the bit is set, then the invention executes an integer exponentiation routine to calculate a.sup.x directly in the math core. If, however, the bit is not set, then the invention executes a floating point exponentiation routine to closely approximate the calculation of a.sup.x.

Abstract: The present invention provides a method and apparatus for processing primitives in a computer graphics display system. The present invention comprises a geometry accelerator for processing polygons to provide two-sided lighting for front and back facing polygons. The geometry accelerator comprises a lighting machine and a memory device in communication with the lighting machine. The geometry accelerator receives command data, vertex data, and parameter data from a central processing unit (CPU) of a computer graphics display system. The vertex data comprises polygon vertex color data, vertex coordinate data and vertex normal data. The parameter data comprises front and back material parameters. The command data comprises information relating to the type of primitive to be processed by the lighting machine.

Abstract: A system and method for performing speculative execution of state machine operation in a graphics accelerator. In accordance with one aspect of the invention, the method includes the step of executing steps in a first state machine that is operating on a graphic primitive. As is known, a graphic primitive is defined by a plurality of vertices. In accordance with the invention, the preferred embodiment receives the coordinate parameters for the second to last primitive vertex. Then it evaluates one or more conditions that indicate whether steps in a second state machine need to be executed, based upon parameters of primitive vertices already received. It then branches to and begins executing steps in another state machine, based upon the tentative conditions, and continuing execution of the steps in the transformation state machine in parallel with the continued execution of the steps in the another state machine.

Abstract: Apparatus for electrically verifying a functional unit contained within an integrated circuit comprises a functional unit, a state machine, a number of integrated circuit input pins, and means for alternately providing the functional unit with control data derived from the state machine, and control data derived from the number of integrated circuit input pins. The means for providing control data from alternating sources comprises a multiplexor which receives a first set of inputs from the state machine, and a second set of inputs from a test control block. The test control block monitors various of the integrated circuit input pins for a designated instruction, receives control data via the input pins, and controls the operation of the multiplexor. The test control block comprises a number of test registers which can be configured to receive two or more states of control data.

Abstract: An enhanced test system in a processor having a memory supporting multiple memory schemes. The memory is partitioned into memory blocks and memory sub-blocks. A plurality of uniform data units each comprising a plurality of data fields is written to and read from each successive memory block in a FIFO manner so that a data field within each data unit, having a maximum field width, occupies each of the multiple memory locations at least once during testing. The enhanced test system maximizes the number of adjacent full-width data fields to test vertically and horizontally for field overflow within memory by writing and reading seriatim by data unit or partitioned by data field width, in adjacent memory blocks and sub-blocks, or overlapping memory blocks and overlapping sub-blocks.

Abstract: A computer graphics system includes a plurality of geometry accelerators for processing vertex data representative of graphics primitives and providing rendering data. The system includes a distributor responsive to a stream of vertex data for distributing to the geometry accelerators chunks of the vertex data for processing by the geometry accelerators to provide chunks of rendering data. The distributor generates an end of chunk bit indicative of the end of each of the chunks of vertex data. The system further includes a concentrator for receiving the chunks of rendering data from each of the geometry accelerators and for combining the chunks of rendering data into a stream of rendering data in response to end of chunk bits. The stream of rendering data and the stream of vertex data represent sequences of graphics primitives having the same order. A rasterizer generates pixel data representative of a graphics display in response to the stream of rendering data.

Abstract: A geometry accelerator for a computer graphics system performs transformations on vertex data representative of graphics primitives, decomposes quadrilaterals into triangles, and performs lighting, clipping and plane equation calculations for each primitive. The geometry accelerator incorporates a memory mapping technique that achieves high efficiency transfer of vertex information from the host computer to the geometry accelerator. A double buffered vertex RAM with granularity permits the quantity of data transferred to the geometry accelerator to be reduced. The transformation and decomposition engines of the geometry accelerator employ data management techniques in which calculations for shared vertices and shared edges of primitives are performed only once.

Abstract: A minimal logic multiplexer system using tri-state drivers with one-hot enabling lead, provides high-speed access to processor elements by any one of a plurality of control units. The multiplexer system is implemented in a manner that minimizes the circuit implementation, minimizes gate delay within the circuit implementation, and allows processing instructions to pass from a control unit to the processor elements by way of multiplexed control lines therebetween. The multiplexer system contains control unit gate groups that are enabled and disabled in parallel by a select lead. Each control unit gate group can be implemented internal to the respective control unit or external in a common intermediary multiplexer circuit location.

Abstract: A geometry accelerator for a computer graphics system performs transformations on vertex data representative of graphics primitives, decomposes quadrilaterals into triangles, and performs lighting, clipping and plane equation calculations for each primitive. The geometry accelerator incorporates a memory mapping technique that achieves high efficiency transfer of vertex information from the host computer to the geometry accelerator. A double buffered vertex RAM with granularity permits the quantity of data transferred to the geometry accelerator to be reduced. The transformation and decomposition engines of the geometry accelerator employ data management techniques in which calculations for shared vertices and shared edges of primitives are performed only once.

Abstract: A hardware graphics accelerator accepts lists of polygon vertices from an application environment running application and systems graphics software. After a polygon is rotated and translated as needed, it is checked for trivial accept/reject against the clip limits of the viewing volume, but is not otherwise clipped. Polygons that are not rejected are decomposed into triangles before any other operations on them are performed. After decomposition the triangles are illuminated by light sources, if desired and then clipped by a triangle clipper, rasterized, and the results sent to a frame buffer for display. The triangle clipper incorporates trivial accept/reject operation, and is capable of operating on non-planar quadrilaterals. It avoids ugly artifacts during certain clip operations when the diagonal used to decompose a quadrilateral into triangles intersects a clip plane not parallel to the viewing axis.

Abstract: A geometry accelerator for a computer graphics system performs transformations on vertex data representative of graphics primitives, decomposes quadrilaterals into triangles, and performs lighting, clipping and plane equation calculations for each primitive. The geometry accelerator incorporates a memory mapping technique that achieves high efficiency transfer of vertex information from the host computer to the geometry accelerator. A double buffered vertex RAM with granularity permits the quantity of data transferred to the geometry accelerator to be reduced. The transformation and decomposition engines of the geometry accelerator employ data management techniques in which calculations for shared vertices and shared edges of primitives are performed only once.

Abstract: An enhanced performance queuing system that includes a FIFO queue in an electronic device, where the FIFO queue is controlled by a FIFO queue controller that also provides FIFO queue status relating to space available in the FIFO queue. A first device writes data to the FIFO queue in data chunks or in data item increments within a data chunk. FIFO queue status is requested only to determine if a data chunk sized space is free prior to writing to a data chunk space in the FIFO queue, rather than polling for FIFO queue status prior to each write operation. A second device reads data from the FIFO queue in data chunks or data item increments from within a data chunk. The first device begins writing to the FIFO queue prior to signaling the second device to begin reading, so that the second device can read from the FIFO queue without ever catching up with the first device thereby eliminating the need for requesting FIFO queue status to determine if data is available for reading.

Abstract: An enhanced test system in a processor having a memory supporting multiple memory schemes. The memory is partitioned into memory blocks and memory sub-blocks. A plurality of uniform data units each comprising a plurality of data fields is written to and read from each successive memory block in a FIFO manner so that a data field within each data unit, having a maximum field width, occupies each of the multiple memory locations at least once during testing. The enhanced test system maximizes the number of adjacent full-width data fields to test vertically and horizontally for field overflow within memory by writing and reading seriatim by data unit or partitioned by data field width, in adjacent memory blocks and sub-blocks, or overlapping memory blocks and overlapping sub-blocks.