Abstract: A partial-blocking consistency point system identifies transaction updates with a consistency point ID associated with a consistency point sequence number, records consistency point data that identify a location of the partial-blocking consistency point, flushes to a non-volatile storage the transaction updates identified with the consistency point sequence number without blocking transaction activity, and hardens to the non-volatile storage the recorded partial-blocking consistency point so that data associated with the recorded partial-blocking consistency point can be recovered. The consistency point sequence number is incremented each time the partial-blocking consistency point is recorded to uniquely identify the partial-blocking consistency point and transaction updates associated with the partial-blocking consistency point. The transaction updates identified with the consistency point sequence number are processed to improve efficiency of the flushing of the transaction updates.

Abstract: A three-dimensional object is manufactured from a powder of polymer material by selective sintering process by means of electromagnetic radiation of the powder, wherein the powder comprises a preselected polymer or copolymer and is subjected to selective sintering such that the manufactured three-dimensional object has a final crystallinity which is in such a range that the balance of properties, in particular mechanical properties including Young's modulus, tensile strength and elongation at break, is improved.

Abstract: The invention relates to improvements in hubs for wall mounting systems for screens, and in particular to a hub for a wall mounting system for a flat panel screen, such as a plasma display or television screen, which enables the screen to be tilted. The hub comprises a casing, means for attaching the hub to a screen bracket, means for attaching the hub to an arm of a wall mount, and a tilt member. The tilt member has a sliding member which is located within an arcuate cavity in the casing such that the sliding member and casing are slidable relative to each other to enable a screen attached to the mounting system to be tilted about a horizontal pivot axis. The arc is defined by the cavity having its centre, which forms the pivot axis, offset from the centre of gravity of the screen. The hub further comprises a compression spring located within the casing and biased to provide a counterbalancing force so that the screen remains stationery in any position.

Abstract: The invention relates to improvements in tiltable wall mounts, and in particular to a self-locking tiltable wall mount for a screen, such as a plasma display or television screen. The tiltable wall mount for a screen comprises wall attachment means for attaching the mount to a substantially vertical surface and screen attachment means for attaching a screen to the mount. The screen attachment means are pivotally connected at one end to one end of the wall attachment means. The wall mount also has a tilt mechanism interconnecting the mount and screen attachment means, said tilt mechanism comprising a locking device comprising at least one cam follower which is biased into abutment with a stepped cam surface projecting from the wall attachment means to prevent relative movement between the wall and screen attachment means.

Abstract: A method and system in accordance with the present invention comprises a thread stack/thread heap combination, wherein the thread heap is for thread local memory usage and wherein the thread stack and thread heap grow in opposite directions. In the present invention the thread specific heap is allocated next to the thread's stack and grows in the opposite direction from that of the stack. This improvement allows the current space management of thread stacks, which spread out the memory placement of multiple stacks to avoid collision, to also be used for the heaps without additional overhead or complexity. It also allows the existing growth scheme of adding memory pages to the process for the stack to be used again because the growth is simply in the opposite direction. Thread specific heaps eliminate the need for expensive synchronization when allocating from a shared heap in a multiprocessor environment.

Abstract: A method of fitting a compressed component, for example a pipe, in a receiver, for example a bore, comprises compressing a selected component which is made out of a polymeric material having a glass transition temperature of at least 100° C., for example polyetheretherketone; arranging the compressed component in position within a receiver; and subjecting the compressed component to conditions, for example of temperature and/or pressure, whereby the compressed component expands.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire.

Abstract: Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

Abstract: A partial-blocking consistency point system identifies transaction updates with a consistency point ID associated with a consistency point sequence number, records consistency point data that identify a location of the partial-blocking consistency point, flushes to a non-volatile storage the transaction updates identified with the consistency point sequence number without blocking transaction activity, and hardens to the non-volatile storage the recorded partial-blocking consistency point so that data associated with the recorded partial-blocking consistency point can be recovered. The consistency point sequence number is incremented each time the partial-blocking consistency point is recorded to uniquely identify the partial-blocking consistency point and transaction updates associated with the partial-blocking consistency point. The transaction updates identified with the consistency point sequence number are processed to improve efficiency of the flushing of the transaction updates.

Abstract: Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy over a target frequency. The image sensor dies can include an image sensor and a corresponding lens device positioned proximate to the image sensor. The method can further include positioning standoffs adjacent to the lens devices while the image sensor dies are connected to each other via the imager workpiece. At least one transmissive element can be attached to the workpiece at least proximate to the standoffs so the lens devices are positioned between the corresponding image sensors and the at least one transmissive element. Accordingly, the at least one transmissive element can protect the image sensors while the image sensor dies are still connected.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from the back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked-systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Abstract: A system that provides fault tolerance in a parallel processing system. During operation, the system executes a parallel computing application in parallel across a subset of computing nodes within the parallel processing system. During this process, the system monitors telemetry signals within the parallel processing system. The system analyzes the monitored telemetry signals to determine if the probability that the parallel processing system will fail is increasing. If so, the system increases the frequency at which the parallel computing application is checkpointed, wherein a checkpoint includes the state of the parallel computing application at each computing node within the parallel processing system.

Abstract: One embodiment of the present invention provides a system that enhances throughput and fault-tolerance in a parallel-processing system. During operation, the system first receives a task. Next, the system partitions N computing nodes into M set-aside nodes and N-M primary computing nodes, wherein M?1. The system then processes the task in parallel across the N-M primary computing nodes. While doing so, the system proactively monitors the health of each of the N-M primary computing nodes. If the system detects a node in the N-M primary computing nodes to be at risk of failure, the system copies the portion of the task associated with the at-risk node to a subset of the M set-aside nodes. The system then processes the portion of the task in parallel across the subset of the M set-aside nodes while the N-M primary computing nodes continue executing.

Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with the protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract: A method for modifying or fabricating one or more interposers includes fabricating a fence on a substrate that includes the one or more interposers. The fence may be fabricated on a single surface of the interposer substrate. Alternatively, a fence and associated features may be fabricated on both opposite surfaces of the interposer substrate, for example, by fabricating features on one surface of the substrate, inverting the substrate, and forming features on the opposite surface of the substrate. The fence, a portion thereof, or associated features or portions thereof may be fabricated by selectively consolidating previously unconsolidated material. Such selective consolidation may be effected under control of a program. Additionally, the selective consolidation may occur in conjunction with a machine vision system.