Patents by Inventor Alana Nakata
Alana Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10600674Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.Type: GrantFiled: April 18, 2019Date of Patent: March 24, 2020Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan T. Strydom, Alana Nakata, Guangyuan Zhao
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Publication number: 20190252238Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.Type: ApplicationFiled: April 18, 2019Publication date: August 15, 2019Inventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan T. Strydom, Alana Nakata, Guangyuan Zhao
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Patent number: 10312131Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.Type: GrantFiled: February 16, 2017Date of Patent: June 4, 2019Assignee: Efficient Power Converson CorporationInventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan T. Strydom, Alana Nakata, Guangyuan Zhao
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Patent number: 10312335Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.Type: GrantFiled: July 20, 2017Date of Patent: June 4, 2019Assignee: Efficient Power Conversion CorporationInventors: Jianjun Cao, Alexander Lidow, Alana Nakata
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Patent number: 10312260Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.Type: GrantFiled: July 20, 2017Date of Patent: June 4, 2019Assignee: Efficient Power Conversion CorporationInventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. de Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Patent number: 10090274Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.Type: GrantFiled: March 24, 2015Date of Patent: October 2, 2018Assignee: Efficient Power Conversion CorporationInventors: Robert Strittmatter, Seshadri Kolluri, Robert Beach, Jianjun Cao, Alana Nakata
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Patent number: 9837438Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.Type: GrantFiled: December 4, 2015Date of Patent: December 5, 2017Assignee: Efficient Power Conversion CorporationInventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20170330898Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.Type: ApplicationFiled: July 20, 2017Publication date: November 16, 2017Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. de Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20170317179Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.Type: ApplicationFiled: July 20, 2017Publication date: November 2, 2017Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
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Patent number: 9748347Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.Type: GrantFiled: July 30, 2014Date of Patent: August 29, 2017Assignee: Efficient Power Conversion CorporationInventors: Jianjun Cao, Alexander Lidow, Alana Nakata
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Publication number: 20170162429Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan T. Strydom, Alana Nakata, Guangyuan Zhao
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Patent number: 9607876Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.Type: GrantFiled: December 14, 2011Date of Patent: March 28, 2017Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan Strydom, Alana Nakata, Guang Y. Zhao
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Patent number: 9583480Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.Type: GrantFiled: December 3, 2015Date of Patent: February 28, 2017Assignee: Efficient Power Conversion CorporationInventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20170047414Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.Type: ApplicationFiled: July 30, 2014Publication date: February 16, 2017Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
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Patent number: 9331191Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.Type: GrantFiled: July 29, 2014Date of Patent: May 3, 2016Assignee: Efficient Power Conversion CorporationInventors: Stephen L. Colino, Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20160111416Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.Type: ApplicationFiled: December 3, 2015Publication date: April 21, 2016Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20160086980Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.Type: ApplicationFiled: December 4, 2015Publication date: March 24, 2016Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooij, Chunhua Zhou, Seshadri Kolluri, Fang-Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20160035847Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Inventors: Jianjun Cao, Alexander Lidow, Alana Nakata
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Patent number: 9214399Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.Type: GrantFiled: July 30, 2014Date of Patent: December 15, 2015Assignee: Efficient Power Conversion CorporationInventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Patent number: 9214528Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.Type: GrantFiled: July 2, 2014Date of Patent: December 15, 2015Assignee: Efficient Power Conversion CorporationInventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao