Patents by Inventor Alana Nakata
Alana Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9214461Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.Type: GrantFiled: July 29, 2014Date of Patent: December 15, 2015Assignee: Efficient Power Coversion CorporationInventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Patent number: 9171911Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.Type: GrantFiled: July 2, 2014Date of Patent: October 27, 2015Assignee: Efficient Power Conversion CorporationInventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao
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Publication number: 20150270241Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.Type: ApplicationFiled: March 24, 2015Publication date: September 24, 2015Inventors: ROBERT STRITTMATTER, Seshadri Kolluri, Robert Beach, Jianjun Cao, Alana Nakata
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Patent number: 8969918Abstract: An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 ? to 900 ?. In a preferred embodiment, the thickness is 600 ?.Type: GrantFiled: April 8, 2010Date of Patent: March 3, 2015Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao
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Publication number: 20150034962Abstract: An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.Type: ApplicationFiled: July 30, 2014Publication date: February 5, 2015Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Robert Strittmatter, Guangyuan Zhao, Yanping Ma, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20150028384Abstract: A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.Type: ApplicationFiled: July 29, 2014Publication date: January 29, 2015Inventors: Jianjun Cao, Robert Beach, Alexander Lidow, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20150028390Abstract: A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.Type: ApplicationFiled: July 29, 2014Publication date: January 29, 2015Inventors: Stephen L. Colino, Jianjun Cao, Robert Beach, Alexander Lidon, Alana Nakata, Guangyuan Zhao, Yanping Ma, Robert Strittmatter, Michael A. De Rooji, Chunhua Zhou, Seshadri Kolluri, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao, Agus Jauhar
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Publication number: 20150008442Abstract: An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.Type: ApplicationFiled: July 2, 2014Publication date: January 8, 2015Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guang Yuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang, Ming-Kun Chiang, Jiali Cao
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Publication number: 20150011057Abstract: A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.Type: ApplicationFiled: July 2, 2014Publication date: January 8, 2015Inventors: Chunhua Zhou, Jianjun Cao, Alexander Lidow, Robert Beach, Alana Nakata, Robert Strittmatter, Guang Yuan Zhao, Seshadri Kolluri, Yanping Ma, Fang Chang Liu, Ming-Kun Chiang, Jiali Cao
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Patent number: 8890168Abstract: An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.Type: GrantFiled: March 15, 2013Date of Patent: November 18, 2014Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuang Zhao
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Patent number: 8853749Abstract: A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.Type: GrantFiled: January 31, 2012Date of Patent: October 7, 2014Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Jianjun Cao, Robert Beach, Robert Strittmatter, Guang Y. Zhao, Alana Nakata
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Patent number: 8823012Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.Type: GrantFiled: February 23, 2012Date of Patent: September 2, 2014Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao, Robert Strittmatter, Fang Chang Liu
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Patent number: 8785974Abstract: A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.Type: GrantFiled: April 8, 2010Date of Patent: July 22, 2014Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao
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Publication number: 20130234153Abstract: An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.Type: ApplicationFiled: March 15, 2013Publication date: September 12, 2013Applicant: Efficient Power Conversion CorporationInventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuang Zhao
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Patent number: 8404508Abstract: An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.Type: GrantFiled: April 8, 2010Date of Patent: March 26, 2013Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao
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Patent number: 8350294Abstract: A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.Type: GrantFiled: April 8, 2010Date of Patent: January 8, 2013Assignee: Efficient Power Conversion CorporationInventors: Alexander Lidow, Robert Beach, Jianjun Cao, Alana Nakata, Guang Yuan Zhao
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Publication number: 20120193688Abstract: A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Inventors: Alexander Lidow, Jianjun Cao, Robert Beach, Robert Strittmatter, Guang Y. Zhao, Alana Nakata
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Publication number: 20120175631Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.Type: ApplicationFiled: February 23, 2012Publication date: July 12, 2012Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao, Robert Strittmatter, Fang Chang Liu
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Publication number: 20120153300Abstract: Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.Type: ApplicationFiled: December 14, 2011Publication date: June 21, 2012Inventors: Alexander Lidow, Jianjun Cao, Robert Beach, Johan Strydom, Alana Nakata, Guang Y. Zhao
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Patent number: 8102668Abstract: An integral impedence is formed on or within a lead frame pin of a semiconductor package and receives a connection from an electrode of a semiconductor die within the package to eliminate the need for adjustment and protective impedences external of the package. The impedence comprises passives such as resistors, capacitors, diodes or inductors which modify the performance of the package for new semiconductor device characteristics. The impedences may have positive or negative temperature coefficients and are in close thermal communication with the semiconductor die.Type: GrantFiled: May 6, 2008Date of Patent: January 24, 2012Assignee: International Rectifier CorporationInventors: Henning M. Hauenstein, Alana Nakata