Abstract: Processing circuitry (16) and an instruction decoder (9) supports a load chunk instruction and a store chunk instruction which can be useful for implementing memory copy functions and other library functions for manipulating or comparing blocks of memory. Number of bytes to load or store in response to these instructions is determined based on an implementation specific condition. As well as loading or storing bytes of data, the load chunk instruction and (10) store chunk instruction also designated a load/store length value as data corresponding to an architecturally visible register, which provides an indication of a number of bytes loaded or stored.

Abstract: An apparatus and method are provided for handling transactions in a system employing transactional memory. The apparatus has processing circuitry for performing data processing in response to instructions, and transactional memory support circuitry for supporting execution of a transaction within a thread of data processing by the processing circuitry. The transaction comprises a sequence of instructions executed speculatively and for which the processing circuitry prevents commitment of results of those instructions until the transaction has reached a transaction end point. The transactional memory support circuitry comprises abort event detection circuitry that causes execution of the transaction to be aborted when an abort event is detected before the transaction has reached the transaction end point, and which causes abort status information to be stored for later reference when determining whether to retry execution of the transaction.

Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

Abstract: A first processor for executing program code has a control interface mapped to the memory address space of a second processor and provides the second processor with direct mapped access to state information of the first processor. The first processor responds to an exception causing event to enter a halted mode stopping execution of the program code and issuing a trigger event. The second processor responds to the trigger to execute an exception handling routine during which the second processor accesses and modifies the state information via the control interface as required by the exception handling routine. On completion of the exception handling routine, the second processor causes the first processor to exit the halted mode and resume execution of the program code. Thus, the program code is physically separated from the software used to perform the exception handling routine to improve security.

Abstract: Processing circuitry performs data processing operations in response to instructions fetched from a cache or memory or micro-operations decoded from the instructions. Sampling circuitry selects a subset of instructions or micro-operations as sampled operations to be profiled. Profiling circuitry captures, in response to processing of an instruction or micro-operation selected as a sampled operation, a sample record specifying an operation type of the sampled operation and information about behaviour of the sampled operation which is directly attributed to the sampled operation. The profiling circuitry can include, in the sample record for a sampled operation corresponding to a given instruction, a reference instruction address indicator indicative of an address of a reference instruction appearing earlier or later in program order than the given instruction, for which control flow is sequential between any instructions occurring between the reference instruction and the given instruction in program order.

Abstract: A method for separating of at least two transition metals, the method comprising: injecting a feed solution into a chromatography column comprising a chromatographic support media, the feed solution comprising at least two transition metals; eluting the feed from the column in an elution cycle by flowing an eluent through the column, wherein a concentration of the eluent is reduced during the elution cycle prior to elution of at least one of the transition metals.

Abstract: Apparatuses and methods of operating such apparatuses are disclosed. Vector processing circuitry performs data processing in multiple parallel processing lanes, wherein the data processing is performed in a subset of the multiple parallel processing lanes determined by bit values of a vector predicate which are set. Predicate monitoring circuitry is responsive to the vector predicate to generate a predicate summary value in dependence on the bit values of the vector predicate. A first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition being true when the bit values of the vector predicate comprise a set bit corresponding to a vector element at a higher index immediately followed by a non-set bit corresponding to a vector element at a lower index. A second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate. Improved predicate controlled vector processing is thus supported.

Abstract: There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry.

Abstract: An apparatus and method are described for aligning corresponding elements in multiple streams of elements. An apparatus is provided comprising both first generation circuitry to generate a first stream comprising first elements and second generation circuitry to generate a second stream comprising second elements. The first generation circuitry is arranged to insert a first element in the first stream to identify each occurrence of a corresponding second element in the second stream. Key generation circuitry is used to generate, for each instance of the first element to be included within the first stream, an associated key value determined from a set of key values, the set of key values being insufficient to allow unique key values to be generated for each instance of the first element. The first generation circuitry is then arranged to indicate within the first stream the associated key value for each instance of the first element.

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

Abstract: Apparatuses and methods of operating such apparatuses are disclosed. Vector processing circuitry performs data processing in multiple parallel processing lanes, wherein the data processing is performed in a subset of the multiple parallel processing lanes determined by bit values of a vector predicate which are set. Predicate monitoring circuitry is responsive to the vector predicate to generate a predicate summary value in dependence on the bit values of the vector predicate. A first value of the predicate summary value indicates that a sparse condition is true for the vector predicate, the sparse condition being true when the bit values of the vector predicate comprise a set bit corresponding to a vector element at a higher index immediately followed by a non-set bit corresponding to a vector element at a lower index. A second value of the predicate summary value indicates that the sparse condition is not true for the vector predicate. Improved predicate controlled vector processing is thus supported.

Abstract: A barrier-free atomic transfer method of multiword data is described. In the barrier-free method, a producer processor deconstructs an original parameter set of data into a deconstructed parameter set; and performs a series of single-copy-atomic writes to a series of single-copy-atomic locations. Each single-copy-atomic location in the series of single-copy-atomic locations comprises a portion of the deconstructed parameter set and a sequence number. A consumer processor can read the series of single-copy-atomic locations; verifies that the sequence number for each single-copy-atomic location in the series of single-copy-atomic locations is consistent (e.g., are all the same sequence number); and reconstructs the portions of deconstructed parameter set into the original parameter set.

Abstract: An apparatus and method are provided for handling exception causing events. A first processing unit is provided for executing program code, and a second processing unit is also provided. The first processing unit has a control interface mapped to the memory address space of the second processing unit and configured to provide the second processing unit with direct mapped access to state information of the first processing unit. The first processing unit is responsive to at least one exception causing event to enter a halted mode where the first processing unit stops execution of the program code and issues a trigger event. The second processing unit is responsive to the trigger event to execute an exception handling routine during which the second processing unit is arranged to access the state information of the first processing unit via the control interface in order to modify the state information as required by the exception handling routine.

Abstract: There is provided execution circuitry. Storage circuitry retains a stored state of the execution circuitry. Operation receiving circuitry receives, from issue circuitry, an operation signal corresponding to an operation to be performed that accesses the stored state of the execution circuitry from the storage circuitry. Functional circuitry seeks to perform the operation in response to the operation signal by accessing the stored state of the execution circuitry from the storage circuitry. Delete request receiving circuitry receives a deletion signal and in response to the deletion signal, deletes the stored state of the execution circuitry from the storage circuitry. State loss indicating circuitry responds to the operation signal when the stored state of the execution circuitry is not present and is required for the operation by indicating an error. In addition, there is provided a data processing apparatus comprising issue circuitry to issue an operation to execution circuitry.

Abstract: Trace circuitry 22, 6 forms trace objects 34 representing a sequence of executed program instructions and comprising a start address indicator indicating a start address of a sequence of executed program instructions, a branch outcome indicator indicating a sequence of branch outcomes within the sequence of executed program instructions starting from the start address and a count indicator indicating a count of times the sequence of branch outcomes was detected. The trace circuitry may be on-chip 22 or off-chip 6. A trace object may include an indicator of a start address of a next sequence of program instructions to be followed following the sequence of program instructions represented by the trace object concerned.

Abstract: An apparatus and method are described for aligning corresponding elements in multiple streams of elements. An apparatus is provided comprising both first generation circuitry to generate a first stream comprising first elements and second generation circuitry to generate a second stream comprising second elements. The first generation circuitry is arranged to insert a first element in the first stream to identify each occurrence of a corresponding second element in the second stream. Key generation circuitry is used to generate, for each instance of the first element to be included within the first stream, an associated key value determined from a set of key values, the set of key values being insufficient to allow unique key values to be generated for each instance of the first element. The first generation circuitry is then arranged to indicate within the first stream the associated key value for each instance of the first element.

Abstract: Data processing circuitry comprises a processing element configured to perform processing activities; a trace data store; and trace circuitry to generate items of trace data indicative of processing activities of the processing element and to store the items of trace data in the trace data store; the trace circuitry comprising detection circuitry to detect a condition relating to an outcome of a given processing activity for which items of trace data have been stored in the trace data store and to selectively discard at least some of the stored items of trace data relating to the given processing activity in dependence upon the detected condition.

Abstract: There is provided an apparatus that includes processing circuitry for performing processing operations specified by program instructions and a target register that stores a target program address. A value register stores a data value. There is also provided an architectural register and an instruction decoder that decodes the program instructions to generate control signals to control the processing circuitry to perform the processing operations. The instruction decoder includes branch instruction decoding circuitry that decodes a register restoring branch instruction to cause the processing circuitry to determine whether the target program address and the data value are valid. If the target program address and the data value are both valid then the processing circuitry is caused to branch to the target program address and update the architectural register to store the data value. Otherwise an error action is taken.

Abstract: Apparatuses and methods of their operation are disclosed. A call stack is maintained which comprises subroutine information relating to subroutines which have been called during data processing operations and have not yet returned. A stack pointer is indicative of an extremity of the call stack associated with a most recently called subroutine which has been called during the data processing operations and has not yet returned. Call stack sampling can be carried out with reference to the stack pointer. A tide mark pointer is maintained, which indicates of a value which the stack pointer had when the call stack sampling procedure processing circuitry was last completed. The call stack sampling procedure comprises retrieving subroutine information from the call stack indicated between the value of the tide mark pointer and the current value of the stack pointer. More efficient call stack sampling is thereby supported, in that only modifications to the call stack need be sampled.

Abstract: Aspects of the present disclosure relate to an apparatus comprising a requester master processing device having an associated private cache storage to store data for access by the requester master processing device. The requester master processing device is arranged to issue a request to modify data that is associated with a given memory address and stored in a private cache storage associated with a recipient master processing device. The private cache storage associated with the recipient master processing device is arranged to store data for access by the recipient master processing device. The apparatus further comprises the recipient master processing device having its private cache storage. One of the recipient master processing device and its associated private cache storage is arranged to perform the requested modification of the data while the data is stored in the cache storage associated with the recipient master processing device.