Abstract: Apparatuses and methods of their operation are disclosed. A call stack is maintained which comprises subroutine information relating to subroutines which have been called during data processing operations and have not yet returned. A stack pointer is indicative of an extremity of the call stack associated with a most recently called subroutine which has been called during the data processing operations and has not yet returned. Call stack sampling can be carried out with reference to the stack pointer. A tide mark pointer is maintained, which indicates of a value which the stack pointer had when the call stack sampling procedure processing circuitry was last completed. The call stack sampling procedure comprises retrieving subroutine information from the call stack indicated between the value of the tide mark pointer and the current value of the stack pointer. More efficient call stack sampling is thereby supported, in that only modifications to the call stack need be sampled.

Abstract: A cache interconnect and method of operating a cache interconnect are disclosed. In the cache interconnect snoop circuitry stores a table containing an entry, for each of a plurality of cache lines, comprising a cache line identifier, an indication of a most recent processing element of a plurality of processing elements associated with the cache interconnect to access the cache line, and an indication of a data item in the cache line which was identified by the most recent processing element to be accessed. In response to a request from a requesting processing element of the plurality of processing elements, the request identifying a requested data item, the snoop circuitry determines a requested cache line identifier corresponding to the requested data item and looks up that identifier in the table.

Abstract: An apparatus comprises processing circuitry for accessing data in a physically-indexed cache. Set indicator recording circuitry is provided to record a set indicator corresponding to a target physical address, where the set indicator depends on which set of one or more storage locations of the cache corresponds to the target physical address. The set indicator is insufficient to identify the target physical address itself. This enables performance issues caused by contention of data items for individual sets in a physically-indexed set-associative or direct-mapped cache to be identified without needing to expose the physical address itself to potentially insecure processes or devices.

Abstract: A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.

Abstract: Data processing apparatus comprises a processing element having an instruction pipeline to execute instructions and trace circuitry to generate items of trace data indicative of processing activities of the processing element. The trace circuitry generates items of event trace data in response to events initiated by execution of corresponding instructions by the instruction pipeline and also generates items of waypoint trace data in response to instructions, in a set of waypoint instructions, reaching a predetermined stage relative to the instruction pipeline. The trace circuitry generates position data, indicating a relative position with respect to execution of the corresponding instructions by the instruction pipeline, of one or more items of event trace data and one or more items of waypoint trace data.

Abstract: Aspects of the present disclosure relate to an apparatus comprising a requester master processing device having an associated private cache storage to store data for access by the requester master processing device. The requester master processing device is arranged to issue a request to modify data that is associated with a given memory address and stored in a private cache storage associated with a recipient master processing device. The private cache storage associated with the recipient master processing device is arranged to store data for access by the recipient master processing device. The apparatus further comprises the recipient master processing device having its private cache storage. One of the recipient master processing device and its associated private cache storage is arranged to perform the requested modification of the data while the data is stored in the cache storage associated with the recipient master processing device.

Abstract: A cache interconnect and method of operating a cache interconnect are disclosed. In the cache interconnect snoop circuitry stores a table containing an entry, for each of a plurality of cache lines, comprising a cache line identifier, an indication of a most recent processing element of a plurality of processing elements associated with the cache interconnect to access the cache line, and an indication of a data item in the cache line which was identified by the most recent processing element to be accessed. In response to a request from a requesting processing element of the plurality of processing elements, the request identifying a requested data item, the snoop circuitry determines a requested cache line identifier corresponding to the requested data item and looks up that identifier in the table.

Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.

Abstract: A barrier-free atomic transfer method of multiword data is described. In the barrier-free method, a producer processor deconstructs an original parameter set of data into a deconstructed parameter set; and performs a series of single-copy-atomic writes to a series of single-copy-atomic locations. Each single-copy-atomic location in the series of single-copy-atomic locations comprises a portion of the deconstructed parameter set and a sequence number. A consumer processor can read the series of single-copy-atomic locations; verifies that the sequence number for each single-copy-atomic location in the series of single-copy-atomic locations is consistent (e.g., are all the same sequence number); and reconstructs the portions of deconstructed parameter set into the original parameter set.

Abstract: The invention relates to processes for separating metals, and in particular for separating precious metals such as platinum and palladium, by solvent extraction. The invention also provides novel solvent extraction mixtures useful in the processes of the invention. The inventors have found that by simultaneously employing different extraction mechanisms for the extraction of a plurality of different metals, a simple and convenient process for their separation can be achieved. In particular, the inventors have found that the use of different extraction mechanisms for simultaneously extracting metals from an aqueous acidic phase into an organic phase enables the extracted metals to be separated by selective stripping from the organic phase using simple and mild conditions. This process is particularly advantageous as it permits two or more metals to be separated following a single solvent extraction step, because of the ability to selectively strip the metals from the organic phase.

Abstract: A data processing system includes decoder circuitry responsive to a performance-steered branch instruction to select between multiple paths through the program in dependence upon performance signals indicative of performance characteristics associated with executing those paths. The performance characteristics may include an indication of whether the path concerned includes events such as a cache miss, a store exclusive failure, triggering of undefined instruction trap, an undesirable power management event, execution of a hint instruction, exceeding a predetermined number of processing cycles etc. The different paths between which a selection has been made can converge at a join instruction. Execution of a join instruction triggers evaluation circuitry to evaluate and store performance characteristics which may subsequently be used to steer the performance-steered branch instruction when it is encountered again.

Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.

Abstract: There is provided an apparatus that includes processing circuitry for performing processing operations specified by program instructions and a target register that stores a target program address. A value register stores a data value. There is also provided an architectural register and an instruction decoder that decodes the program instructions to generate control signals to control the processing circuitry to perform the processing operations. The instruction decoder includes branch instruction decoding circuitry that decodes a register restoring branch instruction to cause the processing circuitry to determine whether the target program address and the data value are valid. If the target program address and the data value are both valid then the processing circuitry is caused to branch to the target program address and update the architectural register to store the data value. Otherwise an error action is taken.

Abstract: A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

Abstract: Data processing circuitry comprises a processing element configured to perform processing activities; a trace data store; and trace circuitry to generate items of trace data indicative of processing activities of the processing element and to store the items of trace data in the trace data store; the trace circuitry comprising detection circuitry to detect a condition relating to an outcome of a given processing activity for which items of trace data have been stored in the trace data store and to selectively discard at least some of the stored items of trace data relating to the given processing activity in dependence upon the detected condition.

Abstract: A data processing system 2 includes decoder circuitry 6 responsive to a performance-steered branch instruction PSB to select between multiple paths through the program in dependence upon performance signals indicative of performance characteristics associated with executing those paths. The performance characteristics may include an indication of whether the path concerned includes events such as a cache miss, a store exclusive failure, triggering of undefined instruction trap, an undesirable power management event, execution of a hint instruction, exceeding a predetermined number of processing cycles etc. The different paths between which a selection has been made can converge at a join instruction 22. Execution of a join instruction triggers evaluation circuitry 18 to evaluate and store performance characteristics which may subsequently be used to steer the performance-steered branch instruction when it is encountered again.

Abstract: An apparatus comprises processing circuitry for accessing data in a physically-indexed cache. Set indicator recording circuitry is provided to record a set indicator corresponding to a target physical address, where the set indicator depends on which set of one or more storage locations of the cache corresponds to the target physical address. The set indicator is insufficient to identify the target physical address itself. This enables performance issues caused by contention of data items for individual sets in a physically-indexed set-associative or direct-mapped cache to be identified without needing to expose the physical address itself to potentially insecure processes or devices.

Abstract: Trace circuitry 22, 6 forms trace objects 34 representing a sequence of executed program instructions and comprising a start address indicator indicating a start address of a sequence of executed program instructions, a branch outcome indicator indicating a sequence of branch outcomes within the sequence of executed program instructions starting from the start address and a count indicator indicating a count of times the sequence of branch outcomes was detected. The trace circuitry may be on-chip 22 or off-chip 6. A trace object may include an indicator of a start address of a next sequence of program instructions to be followed following the sequence of program instructions represented by the trace object concerned.

Abstract: A method for generating a profile of a target program executed by a target data processing apparatus comprises performing at least one profile updating operation. Each profile updating operation includes identifying based on at least one waypoint marker indicating an outcome of a corresponding waypoint instruction of a target program, a next block of instructions executed by the target data processing apparatus during execution of the target program; determining whether a target entry for the next block of instructions is present in a profile cache; when the target entry is present updating the profile of the target program according to zero, one or more profile updating actions specified by the target entry. When the target entry is absent, any profile updating actions can be determined based on an instruction-by-instruction representation of the target program. This approach helps to speed up instruction-based summaries from program flow trace.