Abstract: An in-system programmable (ISP) system can be programmed by remote access from a host programming system. The remote access can be accomplished over a wired data network, a wireless data network, a radio channel, or any combination of the above. In the ISP system, an ISP controller receives control and programming data through the access interface to program ISP devices in accordance with ISP programming conventions. The ISP controller can be provided by an integrated circuit having a microprocessor core.

Abstract: An input/output circuit in an In-system programmable (ISP) logic device allows an output signal from a boundary scan register to be provided as output during programming operations of said ISP logic device. Thus, the ISP logic circuit can provide valid data output to other circuits interfaced to the ISP logic circuit during programming of the ISP logic device, thereby obviating a need to reset the system after reprogramming of the ISP logic device.

Abstract: An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits.

Abstract: A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.

Abstract: A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portion of the programmable logic device.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.

Abstract: An improved programmable logic device is disclosed. In one embodiment, the programmable logic device includes a plurality of I/O cells and a plurality of logic block clusters. Each logic block cluster has a set of logic blocks and a cluster routing pool, which provides programmable connections among the logic blocks and the I/O cells. A global routing pool provides programmable connections among the logic block clusters and the I/O cells. Each logic block includes a programmable logic array with a plurality of outputs. A product term sharing array in the logic block has a plurality of bus lines, each of which is coupled to at least one of the outputs of the programmable logic array. The product term sharing array also includes a plurality of output lines, each of which is coupled to a plurality of programmable interconnections that each provide a connection to one of the bus lines. Each output line of the product term sharing array is coupled to the same number of programmable interconnections.

Abstract: A method for coating a substrate with a radioisotope comprising is disclosed. The method comprises immersing the substrate within a solution containing a .gamma., .beta..sup.+, .alpha. or .beta..sup.- emitting radioisotope, then exposing the immersed substrate to tuned vibrational cavitation (i.e. ultrasonic) to produce a coated substrate, followed by baking the coated substrate at a temperature below the recrystallization temperature of the substrate. Following this step, the substrate is rinsed and dried. Substrates coated using the method of this invention exhibit very low rates of leaching of the coated radioisotope, and are suitable for use within medical applications.

Abstract: A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal.

Abstract: An in-system programmable (ISP) system, having a plurality of ISP devices, can be programmed by remote access from a host controller. The remote access can be accomplished over a wired data network, a wireless data network such as an infra-red data network and a radio wave data network, or a hybrid network including both a wired data network portion and a wireless data network portion. An access interface connects the host controller to an ISP programmer over the wired or wireless communication link. The ISP programmer programs the ISP system in accordance with ISP programming conventions. The ISP programmer can be provided by an integrated circuit having a microprocessor core.

Abstract: A device used to facilitate the making of the connection system of an optical fiber comprises: an upright that supports the gripping of the joining piece associated with holding the connectors in an immobile state with respect to the joining piece during the front polymerization of the connection system; this upright also supporting a fastening system used to hold the connector in an immobile state during the rear polymerization of the connection system and an adjuster capable of causing the pivoting and translation of the joining piece so that it surrounds the solder point located in the rear of the connector, held in an immobile state by the fastening system, to achieve the rear polymerization of the connection system. The device is very useful especially in the field of telecommunications by optical fibers.

Abstract: A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are programably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coupled to each of the output signals from the second OR logic array and the output signals (O.

Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

Abstract: An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.

Abstract: Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages.The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.

Abstract: A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

Abstract: Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existance of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.