Abstract: An integrated robotic dispense system for dispensing a bead of viscous material onto a workpiece according to a bead layout pattern includes a robot subsystem including a robot, a dispensing subsystem including a dispenser attached to a working end of the robot for dispensing the viscous material, and a control subsystem including a robot subsystem control module for moving the working end according to a motion profile, a dispensing subsystem control module for controlling the dispensing according to a dispense profile, and a central control module connected with the subsystem control modules. The central control module is configured for determining the motion and dispense profiles, and for causing the robot subsystem to be moved according to the motion profile and the dispensing subsystem to dispense according to the dispense profile to form a dispensed bead, such that a deviation is minimized between the dispensed bead and the bead layout pattern.

Abstract: The memory device includes a memory block with memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry for optimizing a plurality of read voltages that are associated with a plurality of data states. With a first set of parameters, the circuitry performs a first threshold voltage tracking operation on a selected word line of the plurality of word lines to establish an optimized read voltage for a first data state of the plurality of data states. The circuitry then establishes a second set of parameters as a function of results of the first threshold voltage tracking operation. With the second set of parameters, the circuitry performs a second threshold voltage tracking operation on the selected word line to establish an optimized read voltage for a second data state of the plurality of data states.

Abstract: A memory device includes a set of memory cells and a control circuit coupled to the set of memory cells. The control circuit is configured to transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level. While the wordline voltage settles at the second wordline voltage level, the control circuit cuts off current to the target memory cell by at least one of temporarily ramping down a bitline voltage from a first bitline voltage level to a second bitline voltage level, temporarily ramping down a select gate voltage from a first select gate voltage level to a second select gate voltage level, and temporarily ramping up a source line voltage from a first source level to a second source level.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.

Abstract: A non-volatile memory is capable of suspending a programming process before completion to perform a read (or other) process. When resuming the suspended programming process, a magnitude of a next program voltage pulse is set to be a voltage magnitude of a previous program voltage pulse plus a nominal increment adjusted by a voltage offset in response to the programming process being suspended for greater than a first time period. The magnitude of the next program voltage pulse is set to be the voltage magnitude of the previous program voltage pulse plus the nominal increment in response to the programming process being suspended for less than the first time period. The voltage offset and the first time period are set based on usage of the non-volatile memory (e.g., based on number of program-erase cycles performed).

Abstract: A non-volatile memory stores data in non-volatile memory cells by programming the non-volatile memory cells to a set of data states. Data stored in the non-volatile memory cells is read by sensing for a set of read reference levels for the data states. The read reference levels are adjusted based on performing sense operations at incrementally higher threshold voltages and counting a number of memory cells newly turning on at each sense operation performed until the sooner of a maximum number of sense operations or the count of number of memory cells newly turning on during a current sense operation is greater than the count of number of memory cells newly turning on during a previous sense operation. The system then identifies a valley in the number of memory cells newly turning on and adjusts one or more read reference levels based on the identified valley.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means is configured to determine ones of the data states for the memory cells of a neighboring word line adjacent to a selected word line in a pre-read. The control means determines an adjusted sense time according to a zone identified for the memory cells of the neighboring word line and the one of the data states targeted for the memory cells of the selected word line and a temperature of the memory apparatus. The control means is also configured to perform reads on the selected word line for each of a plurality of groupings of ones of the data states in a read operation using the adjusted sense time determined for each of the memory cells of the selected word line.

Abstract: A non-volatile storage apparatus stores data in the non-volatile memory cells by programming the non-volatile memory cells to a set of data states and reads data stored in the non-volatile memory cells by sensing for a set of read reference levels for the data states. To address data retention issues, including memory cells having the threshold voltages drift over time, one or more of the set of read reference levels are shifted based on sensing the non-volatile memory cells for two different conditions during a single ramping up of a voltage signal applied to the non-volatile memory cells.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged in word lines. The word lines are in electrical communication with respective word line drivers and switches. Control circuitry is configured to program the memory cells of a selected word line in a programming operation during which the control circuitry applies an elevated voltage to the selected word line and receives a command to suspend the programming operation. With the word line switch associated with the selected word line turned on, the control circuitry ramps the selected word line from the elevated voltage to a reduced gate holding voltage and then turn the word line switch associated with the selected word line off to electrically isolate the selected word line from the associated word line driver so that the selected word line remains at the gate holding voltage until the programming operation resumes.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. During programming, the circuitry is configured to, in a program loop, apply a programming pulse at a programming voltage VPGM to a selected word line to program a plurality of the memory cells of the selected word line to a target data state. The circuitry is also configured to suspend the programming operation for a suspension duration and then resume the programming operation. Before a next program loop, the circuitry is further configured to increase a programming voltage VPGM by a step size that is determined based on the suspension duration and on the targeted data state.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory cells are disposed in memory holes grouped in blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed during at least one read operation. The control means adjusts at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the plurality of data states in the at least one read operation.

Abstract: An apparatus comprising a set of memory cells and a control circuit coupled to the set of memory cells is disclosed. The control circuit is configured to: transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level; subsequent to transitioning the wordline voltage to the second wordline voltage level, ramp down a bitline voltage of a bitline associated with the target memory cell from a first bitline voltage level to a second bitline voltage level; and prior to sensing a state of the memory cell, ramp up the bitline voltage from the second bitline voltage level to the first bitline voltage level.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.

Abstract: The present disclosure relates to a cassette and a tissue embedding method using the cassette. The cassette includes a frame, a cover and a base. The frame defines an accommodating cavity through a first face and a second face of the frame arranged oppositely in a first direction. The cover is detachably mounted to the frame. The base is detachably mounted to the frame, and the base and the cover are configured to hold and orient a tissue sample therebetween. The base is slidable relative to the frame in a second direction different from the first direction to open and close the accommodating cavity.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.

Abstract: A system for drawing a solution is provided. The system includes a filter, a vacuum source, and an actuator. The filter has an input port, a first output port, a second output port, and a flow path defined in part by the input port and the second output port. The vacuum source is in fluid communication with the first output port and operative to apply a vacuum to the flow path. The actuator is operative to facilitate movement of the solution along the flow path.

Abstract: A system for drawing a solution is provided. The system includes a filter, a vacuum source, and an actuator. The filter has an input port, a first output port, a second output port, and a flow path defined in part by the input port and the second output port. The vacuum source is in fluid communication with the first output port and operative to apply a vacuum to the flow path. The actuator is operative to facilitate movement of the solution along the flow path.

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

Abstract: A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.