Patents by Inventor Albert M. Chu

Albert M. Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10755017
    Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Laura R. Darden, Albert M. Chu, Alexander J. Suess
  • Patent number: 10693005
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Publication number: 20200020591
    Abstract: A method for forming a semiconductor device includes flipping a vertical transistor including a bottom side having at least one connection to at least one bottom side metallization structure, and, after flipping the vertical transistor, forming at least one top side metallization structure having at least one connection to a top side of the vertical transistor.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Inventors: Brent A. Anderson, Albert M. Chu
  • Publication number: 20200019665
    Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: BRENT A. ANDERSON, LAURA R. DARDEN, ALBERT M. CHU, ALEXANDER J. SUESS
  • Patent number: 10529625
    Abstract: A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Albert M. Chu
  • Patent number: 10424574
    Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Albert M. Chu, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10424576
    Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Albert M. Chu, Myung-Hee Na, Ravikumar Ramachandran
  • Publication number: 20190259869
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10381480
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10381338
    Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Albert M. Chu, Lawrence A. Clevenger, Ximeng Guan, Myung-Hee Na
  • Patent number: 10361128
    Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Albert M. Chu
  • Publication number: 20190097016
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Publication number: 20180308762
    Abstract: A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Inventors: Brent A. Anderson, Albert M. Chu
  • Patent number: 10074570
    Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Albert M. Chu
  • Publication number: 20180211947
    Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
    Type: Application
    Filed: January 23, 2017
    Publication date: July 26, 2018
    Inventors: Albert M. Chu, Myung-Hee Na, Ravikumar Ramachandran
  • Publication number: 20180211948
    Abstract: A method is presented for forming a layout of a MOSFET (metal oxide semiconductor field effect transistor) circuit. The method includes forming a plurality of gate conductors, forming a plurality of active areas, and forming at least one gate contact (CB contact) within an active region of the plurality of active regions. The method further includes placing a marker over the at least one gate contact to identify a location of the at least one gate contact. Additionally, a distance between the at least one gate contact and at least one TS contact is optimized based on device specifications.
    Type: Application
    Filed: November 3, 2017
    Publication date: July 26, 2018
    Inventors: Albert M. Chu, Myung-Hee Na, Ravikumar Ramachandran
  • Publication number: 20180197787
    Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 12, 2018
    Inventors: Brent A. Anderson, Albert M. Chu
  • Publication number: 20180197788
    Abstract: A semiconductor device includes a vertical transistor having a gate structure disposed about a channel region thereof. The vertical transistor has a top side above the gate structure and a bottom side below the gate structure. The top side includes metallization structures having a connection to the vertical transistor on the top side. The bottom side includes metallization structures having a connection to the vertical transistor on the bottom side, and the bottom side includes a power rail and a ground rail.
    Type: Application
    Filed: August 14, 2017
    Publication date: July 12, 2018
    Inventors: Brent A. Anderson, Albert M. Chu
  • Publication number: 20180122792
    Abstract: A semiconductor device includes a substrate and an active area region forming a bottom source/drain region on the substrate. Vertical transistors are formed on the bottom source/drain region, where the bottom source/drain region is shared between the vertical transistors.
    Type: Application
    Filed: February 22, 2017
    Publication date: May 3, 2018
    Inventors: Brent A. Anderson, Albert M. Chu, Terence B. Hook, Seong-Dong Kim
  • Publication number: 20180121593
    Abstract: A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.
    Type: Application
    Filed: May 8, 2017
    Publication date: May 3, 2018
    Inventors: Brent A. Anderson, Albert M. Chu, Terence B. Hook, Seong-Dong Kim