Abstract: A semiconductor IC device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. As a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. The increased landing area further enables the frontside contact to be in further perimeter locations. The inverted gate cut region also results in improved resistance characteristics through the gate structure. Specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. Similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.

Abstract: A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.

Abstract: A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.

Abstract: A semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. The second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.

Abstract: A device comprises memory configured to store program instructions, and processing circuitry, coupled to the memory, and configured to execute the program instructions to perform a process to limit current leakage. The processing circuitry is configured to receive an input of an initial layout of a semiconductor structure comprising a plurality of cells, identify a plurality of edge source/drain regions in respective ones of the cells, determine respective electrical configurations for the edge source/drain regions, compute respective values associated with current leakage for adjacent cells in the initial layout and in a plurality of alternative layouts of the semiconductor structure based at least in part on the respective electrical configurations for the edge source/drain regions, and identify at least one alternative layout of the plurality of alternative layouts to the initial layout that results in at least a reduction of total current leakage from the initial layout.

Abstract: A semiconductor IC device includes an inverted gate cut region with a relatively larger bottom surface area compared to its top surface area. As a result, an associated gate structure may have a relatively larger top contact landing surface area relative to its bottom surface area. The inverted gate cut region may increase a propensity of a frontside gate contact to meld with the gate structure. The increased landing area further enables the frontside contact to be placed in further perimeter locations. The inverted gate cut region also results in improved resistance characteristics through the gate structure. Specifically, the inverted gate cut region enables a wide region between a top channel and the inverted gate cut region that provides a relatively lower electrical resistance therethrough. Similarly, the inverted gate cut region causes a bottom perimeter region with decreased conductive material therein which advantageously results in lower associated parasitic capacitances.

Abstract: A semiconductor structure includes a first circuit row including one or more first circuit cells and a second circuit row including one or more second circuit cells. At a cell boundary between the one or more first circuit cells in the first circuit row and the one or more second circuit cells in the second circuit row, one or more first gate regions of the one or more first circuit cells in the first circuit row are staggered with one or more second gate regions of the one or more second circuit cells in the second circuit row.

Abstract: A semiconductor structure is presented including a plurality of backside supply rails, a primary rail, a first secondary rail and a second secondary rail, wherein the second secondary rail is isolated from the primary rail, and a transistor connecting the first secondary rail to the second secondary rail to supply power therebetween. The primary rail is contiguous only with the second secondary rail. A width of the first and second secondary rails is equal to a width of the primary rail. A supply voltage connection for the first and second secondary rails is provided by a via connected to the primary rail.

Abstract: Embodiments of present invention provide a method of forming backside contact. The method includes forming a set of gate stacks on top of a substrate; forming a first recess in the substrate between the set of gate stacks, the first recess having a triangle shape with a pointy bottom; forming a dielectric anchor at the pointy bottom of the first recess; with the dielectric anchor at the pointy bottom, performing a sigma etch of the substrate through the first recess to form a second recess; epitaxially growing a semiconductor material in the second recess to form a placeholder for a backside contact; surrounding the placeholder with a dielectric material; and replacing the placeholder with a conductive material to form the backside contact. The semiconductor structure formed thereby is also provided.

Abstract: A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.

Abstract: A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate. a backside wiring layer below a backside power delivery network. and a contact via extending between the gate contact and the backside wiring layer.

Abstract: Embodiments of present invention provide an interconnect structure. The structure includes a metal line embedded in a dielectric layer; a first via intersecting with the metal line; and a second via intersecting with the metal line, the second via being horizontally separated from the first via by a length that is less than a blech length of the metal line, where the first and the second via extend vertically at least from a top surface of the metal line to a bottom surface of the metal line and have a width that is equal to or large than a width of the metal line. One or more method of forming the same are also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Abstract: An air pocket is located between a top S/D region and a bottom S/D region of a stacked transistor. The air pocket reduces the parasitic capacitance between the top S/D region and the bottom S/D region, reduces the capacitance between the gate and the top S/D region, and/or reduces the capacitance between the gate and the bottom S/D region. Reduction of such capacitance(s) may improve performance of the semiconductor IC device and may allow for further semiconductor IC device scaling. A semiconductor IC device may include a bottom transistor and a top transistor. The top transistor may be vertically stacked, or aligned, with respect to the bottom transistor. The air pocket is located between, and may be vertically aligned with, the top S/D region and the bottom S/D region.

Abstract: A gate contact is formed within a gate cut region of a semiconductor structure to facilitate electrical routing. The gate contact includes a bottom portion extending within the gate cut region and adjoining a vertical end portion of a metal gate. A metal layer on the front side of the semiconductor structure includes signal tracks, one or more of which is vertically above the gate cut region. A signal track in the metal layer may be electrically connected to the gate contact. Selected source/drain regions within the semiconductor structure may be electrically connected to a back side power delivery network.

Abstract: A semiconductor structure is presented including a power rail having a non-rectangular shape and a middle-of-line (MOL) contact layer electrically connected to the power rail by a metal wiring layer. The non-rectangular shape of the power rail defines at least one notch. Alternatively, the non-rectangular shape of the power rail defines at least one extension. The power rail can be a via rail or a VARAIL.

Abstract: Semiconductor devices and methods of forming the same include a first layer including lower colinear vertical transfer field effect transistors (VTFETs). At least two of the colinear first VTFETs have a first shared bottom source/drain structure. A second layer is positioned over the first layer and includes upper colinear VTFETs. At least two of the upper colinear VTFETs have a second shared bottom source/drain structure.

Abstract: A microelectronic structure including a plurality of nanosheet transistors. Each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers and each of the plurality of nanosheet transistors includes a source/drain region have a first length. The first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. A power via located between a first dummy device and a second dummy device and the power via has second length. The second length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. The second length is larger than the first length.

Abstract: A semiconductor structure including a first stacked transistor structure adjacent to a second stacked transistor structure, and a first conductive structure in direct contact with and electrically connecting a bottom gate conductor of the first stacked transistor structure and a top gate conductor of the second stacked transistor structure.