Patents by Inventor Albert Martinez
Albert Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12019510Abstract: The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.Type: GrantFiled: March 1, 2022Date of Patent: June 25, 2024Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Albert Martinez, Patrick Haddad
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Publication number: 20220283896Abstract: The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.Type: ApplicationFiled: March 1, 2022Publication date: September 8, 2022Applicant: STMICROELECTRONICS (ROUSSET) SASInventors: Albert MARTINEZ, Patrick HADDAD
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Patent number: 11023566Abstract: An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.Type: GrantFiled: October 3, 2018Date of Patent: June 1, 2021Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ROUSSET) SASInventors: Stefano Lunghi, Albert Martinez
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Patent number: 10812327Abstract: Event clusters can in an example embodiment include converting a description of an event associated with a configuration item (CI) to a standardized description, classifying the event based on a comparison of the standardized description of the event with a standardized description of a prior event included in an existing event cluster, and assigning the classified event to an event cluster.Type: GrantFiled: July 31, 2014Date of Patent: October 20, 2020Assignee: ENT. SERVICES DEVELOPMENT CORPORATION LPInventors: Vladimir Ilic, Davor Brajanoski, Volker Messinger, Olivier Gomez, Ricardo Sengenberger, Roman Orlov, Albert Martinez, Jaroslav Furka, Marek Morvai, Marek Horvath, Peter Kluvanec, Juraj Smetana, Michael J. Brandon, Pablo Macaya, Juan Jeronimo Cabello
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Patent number: 10659020Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.Type: GrantFiled: February 8, 2019Date of Patent: May 19, 2020Assignee: STMicroelectronics (Rousset) SASInventors: Jean Nicolai, Albert Martinez
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Publication number: 20200024081Abstract: A system for transporting food items can include a rack having a plurality of shelves for holding and storing the food items, the rack supported on a plurality of wheels so that the rack can be pushed on the wheels. The system can include a shuttle on which the rack can be positioned, the shuttle and rack including features allowing the rack to be locked to and unlocked from the shuttle. The system can include a cooler, a frame, and other components to which the shuttle can be docked and the rack can be transferred from the shuttle. The system can include a robotic arm for loading food items onto the shelves of the rack. The system can include an elevator assembly for loading food items onto the shelves of the rack.Type: ApplicationFiled: July 18, 2019Publication date: January 23, 2020Applicant: Zume, Inc.Inventors: Alexander John Garden, Prashant Ghaiy, Vaibhav Goel, Joshua Gouled Goldberg, Albert Martinez, Justin Osborn, Tim Pletchet, Robert Switek, Tobin Switek, Paul Widergren
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Publication number: 20190190502Abstract: A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.Type: ApplicationFiled: February 8, 2019Publication date: June 20, 2019Applicant: STMicroelectronics (Rousset) SASInventors: Jean NICOLAI, Albert MARTINEZ
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Publication number: 20190114400Abstract: An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.Type: ApplicationFiled: October 3, 2018Publication date: April 18, 2019Inventors: Stefano Lunghi, Albert Martinez
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Patent number: 10243543Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.Type: GrantFiled: November 22, 2016Date of Patent: March 26, 2019Assignee: STMicroelectronics (Rousset) SASInventors: Jean Nicolai, Albert Martinez
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Patent number: 10187040Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.Type: GrantFiled: September 11, 2017Date of Patent: January 22, 2019Assignee: STMicroelectronics (Rousset) SASInventor: Albert Martinez
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Patent number: 10162728Abstract: A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.Type: GrantFiled: July 28, 2016Date of Patent: December 25, 2018Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Albert Martinez
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Patent number: 10103721Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.Type: GrantFiled: November 28, 2016Date of Patent: October 16, 2018Assignee: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan
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Publication number: 20180269855Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.Type: ApplicationFiled: September 11, 2017Publication date: September 20, 2018Applicant: STMicroelectronics (Rousset) SASInventor: Albert Martinez
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Patent number: 10075166Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.Type: GrantFiled: November 28, 2016Date of Patent: September 11, 2018Assignee: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan, Jean Nicolai
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Publication number: 20170324403Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.Type: ApplicationFiled: November 22, 2016Publication date: November 9, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Jean Nicolai, Albert Martinez
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Publication number: 20170324405Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.Type: ApplicationFiled: November 28, 2016Publication date: November 9, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan
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Publication number: 20170324409Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.Type: ApplicationFiled: November 28, 2016Publication date: November 9, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan, Jean Nicolai
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Publication number: 20170228304Abstract: A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.Type: ApplicationFiled: July 28, 2016Publication date: August 10, 2017Inventor: Albert MARTINEZ
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Publication number: 20170134226Abstract: Event clusters can in an example embodiment include converting a description of an event associated with a configuration item (CI) to a standardized description, classifying the event based on a comparison of the standardized description of the event with a standardized description of a prior event included in an existing event cluster, and assigning the classified event to an event cluster.Type: ApplicationFiled: July 31, 2014Publication date: May 11, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Vladimir ILIC, Davor BRAJANOSKI, Volker MESSINGER, Olivier GOMEZ, Ricardo SENGENBERGER, Roman ORLOV, Albert MARTINEZ, Jaroslav FURKA, Marek MORVAI, Marek HORVATH, Peter KLUVANEC, Juraj SMETANA, Michael J. BRANDON, Pablo MACAYA, Juan Jeronimo CABELLO
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Publication number: 20170090801Abstract: A method is for protecting a program code that is executed by a computer processing module having a central processing unit coupled to a cache memory containing cache lines that each have a data field that is intended to store instruction words that can be executed by the central processing unit. The method includes storing the program code in memory locations of an external memory with respect to the computer processing module, each memory location being capable of storing the instruction words of one cache line. The method also includes determining authentication codes that are respectively associated with the cache lines and, for each cache line, fragmenting the associated authentication code and storing this distributed fragmented authentication code in the corresponding memory location.Type: ApplicationFiled: February 23, 2016Publication date: March 30, 2017Inventor: Albert MARTINEZ