Patents by Inventor Albert Martinez
Albert Martinez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10103721Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.Type: GrantFiled: November 28, 2016Date of Patent: October 16, 2018Assignee: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan
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Publication number: 20180269855Abstract: A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.Type: ApplicationFiled: September 11, 2017Publication date: September 20, 2018Applicant: STMicroelectronics (Rousset) SASInventor: Albert Martinez
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Patent number: 10075166Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.Type: GrantFiled: November 28, 2016Date of Patent: September 11, 2018Assignee: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan, Jean Nicolai
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Publication number: 20170324405Abstract: A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.Type: ApplicationFiled: November 28, 2016Publication date: November 9, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan
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Publication number: 20170324409Abstract: A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.Type: ApplicationFiled: November 28, 2016Publication date: November 9, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Michel Agoyan, Jean Nicolai
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Publication number: 20170324403Abstract: A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.Type: ApplicationFiled: November 22, 2016Publication date: November 9, 2017Applicant: STMicroelectronics (Rousset) SASInventors: Jean Nicolai, Albert Martinez
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Publication number: 20170228304Abstract: A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.Type: ApplicationFiled: July 28, 2016Publication date: August 10, 2017Inventor: Albert MARTINEZ
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Publication number: 20170134226Abstract: Event clusters can in an example embodiment include converting a description of an event associated with a configuration item (CI) to a standardized description, classifying the event based on a comparison of the standardized description of the event with a standardized description of a prior event included in an existing event cluster, and assigning the classified event to an event cluster.Type: ApplicationFiled: July 31, 2014Publication date: May 11, 2017Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Vladimir ILIC, Davor BRAJANOSKI, Volker MESSINGER, Olivier GOMEZ, Ricardo SENGENBERGER, Roman ORLOV, Albert MARTINEZ, Jaroslav FURKA, Marek MORVAI, Marek HORVATH, Peter KLUVANEC, Juraj SMETANA, Michael J. BRANDON, Pablo MACAYA, Juan Jeronimo CABELLO
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Publication number: 20170090801Abstract: A method is for protecting a program code that is executed by a computer processing module having a central processing unit coupled to a cache memory containing cache lines that each have a data field that is intended to store instruction words that can be executed by the central processing unit. The method includes storing the program code in memory locations of an external memory with respect to the computer processing module, each memory location being capable of storing the instruction words of one cache line. The method also includes determining authentication codes that are respectively associated with the cache lines and, for each cache line, fragmenting the associated authentication code and storing this distributed fragmented authentication code in the corresponding memory location.Type: ApplicationFiled: February 23, 2016Publication date: March 30, 2017Inventor: Albert MARTINEZ
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Patent number: 9582675Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.Type: GrantFiled: September 30, 2015Date of Patent: February 28, 2017Assignee: STMicroelectronics S.A.Inventors: Albert Martinez, William Orlando
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Publication number: 20160026811Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.Type: ApplicationFiled: September 30, 2015Publication date: January 28, 2016Inventors: Albert Martinez, William Orlando
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Patent number: 9223996Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.Type: GrantFiled: January 28, 2013Date of Patent: December 29, 2015Assignee: STMICROELECTRONICS S.A.Inventors: Albert Martinez, William Orlando
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Patent number: 9019950Abstract: The present disclosure relates to a method for routing data between a sending unit and a receiving unit linked by a network in a processing system comprising several units, the method comprising steps of routing data in the network between the sending unit and the receiving unit, and of applying a process to the routed data, the process comprising several steps which are applied to the data by different units in the network receiving the data, to use latency times in data routing.Type: GrantFiled: May 22, 2009Date of Patent: April 28, 2015Assignee: STMicroelectronics Rousset SASInventor: Albert Martinez
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Patent number: 8902600Abstract: A thermally deformable assembly is formed in an integrated-circuit metallization level. The physical behavior of the metal forming the assembly brings the assembly into contact with a stop-forming body when subjected to a temperature change caused by a current flow. A natural rollback to the initial configuration in which the assembly is a certain distance away from the body is prevented. The state or configuration of the assembly is determined by a capacitive reader.Type: GrantFiled: February 12, 2013Date of Patent: December 2, 2014Assignee: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Pascal Fornara
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Patent number: 8782367Abstract: A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.Type: GrantFiled: December 18, 2007Date of Patent: July 15, 2014Assignee: STMicroelectronics S.A.Inventors: Stéphan Courcambeck, Albert Martinez, Jean Nicolai, William Orlando
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Patent number: 8688983Abstract: A method for transmitting data between a first and a second point comprises the steps of transmitting data, from the first to the second point, together with a signature comprising bits of a first authentication code, and transmitting an acknowledgement, from the second to the first point. The length of the first authentication code is greater than the length of the signature and the first authentication code comprises hidden authentication bits. The acknowledgement is produced by using hidden authentication bits of a second authentication code presumed to be identical to the first, produced at the second point.Type: GrantFiled: April 18, 2012Date of Patent: April 1, 2014Assignee: STMicroelectronics SAInventors: Albert Martinez, William Orlando
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Patent number: 8582757Abstract: A method for protecting the execution of a ciphering or deciphering algorithm against the introduction of a disturbance in a step implementing one or several first values obtained from second values supposed to be invariant and stored in a non-volatile memory in which, during an execution of the algorithm: a current signature of the first values is calculated; this current signature is combined with a reference signature previously stored in a non-volatile memory; and the result of this combination is taken into account at least in the step of the algorithm implementing said first values.Type: GrantFiled: August 26, 2009Date of Patent: November 12, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Yannick Teglia
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Patent number: 8566609Abstract: A method for protecting the integrity of data ciphered by a ciphering algorithm providing at least an intermediary state meant to be identical in ciphering and in deciphering, this intermediary state being sampled during the ciphering to generate a signature.Type: GrantFiled: August 25, 2009Date of Patent: October 22, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Albert Martinez, Yannick Teglia
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Publication number: 20130250531Abstract: A thermally deformable assembly is formed in an integrated-circuit metallization level. The physical behavior of the metal forming the assembly brings the assembly into contact with a stop-forming body when subjected to a temperature change caused by a current flow. A natural rollback to the initial configuration in which the assembly is a certain distance away from the body is prevented. The state or configuration of the assembly is determined by a capacitive reader.Type: ApplicationFiled: February 12, 2013Publication date: September 26, 2013Applicant: STMICROELECTRONICS (ROUSSET) SASInventors: Albert Martinez, Pascal Fornara
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Patent number: 8392726Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.Type: GrantFiled: December 18, 2007Date of Patent: March 5, 2013Assignee: STMicroelectronics S.A.Inventors: Albert Martinez, William Orlando