Patents by Inventor Albert Molina

Albert Molina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus and method for analog-to-digital conversion
    Patent number: 11038516
    Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Ramon Sanchez, Albert Molina, Martin Clara, Daniel Gruber, Matteo Camponeschi
  • Apparatus for calibrating a time-interleaved analog-to-digital converter
    Patent number: 10868556
    Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Matteo Camponeschi, Albert Molina
  • APPARATUS FOR CALIBRATING A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER
    Publication number: 20200313687
    Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes a clock generation circuit configured to generate a plurality of phase shifted clock signals for the plurality of time-interleaved analog-to-digital converter circuits and a reference clock signal. Further, the apparatus includes a reference signal generation circuit configured to generate a reference signal based on the reference clock signal. The reference signal is a square wave signal. The apparatus additionally includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the reference signal generation circuit or to a signal node capable of providing an analog signal for digitization.
    Type: Application
    Filed: February 25, 2020
    Publication date: October 1, 2020
    Inventors: Matteo Camponeschi, Albert Molina
  • n-bit successive approximation register analog-to-digital converter and method for calibrating the same, receiver, base station and mobile device
    Patent number: 10742225
    Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Albert Molina, Martin Clara, Matteo Camponeschi, Christian Lindholm, Kameran Azadet
  • Apparatus for calibrating a time-interleaved analog-to-digital converter
    Patent number: 10601434
    Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration. The analog calibration signal is a wideband signal. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet, Matteo Camponeschi, Jose Luis Ceballos, Christian Lindholm, Hundo Shin, Martin Clara
  • WIRELESS COMMUNICATION TECHNOLOGY, APPARATUSES, AND METHODS
    Publication number: 20200091608
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Application
    Filed: December 20, 2017
    Publication date: March 19, 2020
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Channel estimation using peak cancellation
    Patent number: 10164800
    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet
  • CHANNEL ESTIMATION USING PEAK CANCELLATION
    Publication number: 20180287827
    Abstract: An apparatus and a method for estimation a wireless channel are disclosed. For example, the method correlates, by a correlator, a plurality of signals of a combined signal received by a receive antenna over the wireless channel from a plurality of transmit antennas, with respective DMRSs of the plurality of transmit antennas, converts, by a converter, the correlated plurality of signals from frequency to time domain, iteratively peak cancels, by a peak canceller, a largest peak of the combined impulse response and stores a scaling factor and location pair of the cancelled peak until a magnitude of a next largest peak is below a predetermined threshold, assigns, by an assigner, each of the scaling factor and location pairs to a transmit antenna, and estimates, by an estimator, for each of the plurality of transmit antennas, the wireless channel based on the assigned scaling factor and location pairs.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Albert Molina, Kameran Azadet
  • Methods and apparatus for simultaneous estimation of frequency offset and channel response for MU-MIMO OFDMA
    Patent number: 9942078
    Abstract: Methods and apparatus are provided for simultaneous estimation of frequency offset and channel response for a communication system, such as a MU-MIMO communication system. An iterative method is provided for estimating frequency offset and channel response for a plurality of frequency resources. The channel response is estimated for a set of users sharing a given one of the frequency resources. In addition, the frequency offset is estimated for the users in the set, wherein the channel response and frequency offset of users not in the set are maintained at their latest updated values. Initially, the channel response of a user can be an ideal channel response and the frequency offset can be approximately zero.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: April 10, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Kameran Azadet, Samer Hijazi, Albert Molina, Ramon Sanchez
  • Digital predistortion for dual-band power amplifiers
    Patent number: 9923595
    Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet
  • Software digital front end (SoftDFE) signal processing
    Patent number: 9778902
    Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Chengzhou Li, Albert Molina, Joseph H. Othmer, Steven C. Pinault, Meng-Lin Yu, Joseph Williams, Ramon Sanchez Perez, Jian-Guo Chen
  • Digital processor having instruction set with complex exponential non-linear function
    Patent number: 9529567
    Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Parakalan Venkataraghavan, Meng-Lin Yu, Joseph Williams
  • DIGITAL PREDISTORTION FOR DUAL-BAND POWER AMPLIFIERS
    Publication number: 20160308577
    Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Albert MOLINA, Kameran Azadet
  • Multi-stage crest factor reduction (CFR) for multi-channel multi-standard radio
    Patent number: 9292255
    Abstract: Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of the first and second individual crest factor reduction blocks to generate an aggregated output; and applying the aggregated output to a composite crest factor reduction block. The individual crest factor reduction blocks can be implemented using a sampling rate appropriate for the corresponding technology type. The composite crest factor reduction block operates at a higher sampling rate than the individual crest factor reduction blocks.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Albert Molina
  • Vector processor having instruction set with vector convolution function for fir filtering
    Patent number: 9280315
    Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Meng-Lin Yu, Joseph Othmer, Joseph Williams, Albert Molina
  • Configurable Transmitter Hardware Block and Methods
    Publication number: 20160028514
    Abstract: A configurable transmitter hardware block and corresponding methods for configuring and employing the configurable transmitter hardware block are provided. A configurable transmitter that supports a plurality of channel types comprises a bit selection/manipulation module that performs a bit selection function and/or a bit manipulation function; a modulation mapping module, a gain multiplication module; a spreading/scrambling module that performs a spreading function and/or a scrambling function; and a channel combining module, wherein the configurable transmitter is configured using a plurality of sets of control signals that configure one or more of the modules, wherein each of the sets of control signals are precomputed for a corresponding one of the channel types.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 28, 2016
    Inventors: Parakalan Venkataraghavan, Kannan Rajamani, Sanal Cheruvathery, Albert Molina, Carl Murray, Meng-Lin M. Yu
  • Block-based crest factor reduction (CFR)
    Patent number: 8982992
    Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 17, 2015
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Albert Molina, Joseph H. Othmer, Meng-Lin Yu, Ramon Sanchez Perez
  • Crest factor reduction (CFR) using asymmetrical pulses
    Patent number: 8897388
    Abstract: Crest factor reduction (CFR) techniques are provided using asymmetrical pulses. A crest factor reduction method comprises obtaining one or more data samples; detecting at least one peak in the one or more data samples; performing peak cancellation on the at least one detected peak by applying an asymmetric cancellation pulse to the at least one detected peak; and providing processed versions of the one or more data samples. The asymmetric cancellation pulse is generated, for example, by a minimum phase filter and has a substantially minimum group delay. New peaks associated with peak re-growth are introduced substantially only to the one side of the asymmetric cancellation pulse. The process can optionally rewind by an amount greater than or substantially equal to a group delay of the asymmetric cancellation pulse to address the limited number of pre-cursors that may be present in the asymmetric cancellation pulse.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: November 25, 2014
    Assignee: LSI Corporation
    Inventors: Albert Molina, Kameran Azadet, Chengzhou Li
  • Recursive digital pre-distortion (DPD)
    Patent number: 8831133
    Abstract: Recursive digital pre-distortion (DPD) techniques are provided. Digital pre-distortion is performed by applying a signal to a recursive system to generate a state vector; providing the state vector as a feedback value to the recursive non-linear system; and applying the state vector to a second function to generate an output signal, wherein at least one of the recursive system and the second function comprise a non-linear function. The recursive non-linear system can be initialized to a known initial value. The recursive system is defined by a system of non-linear differential equations.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: September 9, 2014
    Assignee: LSI Corporation
    Inventors: Kameran Azadet, Albert Molina
  • Method for estimating a plurality of estimated transfer functions corresponding to wireless channels in a multiple-input system
    Patent number: 8811927
    Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 19, 2014
    Assignee: Agere Systems LLC
    Inventors: Kameran Azadet, Samer Hijazi, Sunitha Kopparthi, Albert Molina, Ramon Sanchez