Abstract: An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

Abstract: Methods for cleaning and limiting the extent of adhesives are disclosed. For example, a method for cleaning adhesive near a surgical site in a patient's body comprises the acts of dispensing a magnetic adhesive at a desired location at the surgical site, and applying an external magnetic field that removes a portion of the magnetic adhesive from the body of the patient outside of the desired location.

Abstract: Methods for cleaning and limiting the extent of adhesives are disclosed. For example, a method for cleaning adhesive near a surgical site in a patient's body comprises the acts of dispensing a magnetic adhesive at a desired location at the surgical site, and applying an external magnetic field that removes a portion of the magnetic adhesive from the body of the patient outside of the desired location.

Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

Abstract: A vibration-powered impact recording device that harvests power from vibrations that affect the device is provided. The recording device is affixed to an object and includes a vibration limit detection and recordation system. The system can include a suitable part that is fixed to the object, and a mass (or other suitable part) that is less firmly attached, with the relative motion between the two parts producing an electrical voltage. The electrical voltage can be used to power an information storage unit that records the details of the impact and optionally other sensors which record other parameters such as temperature, humidity etc. at the time of impact.

Abstract: A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.

Abstract: A video switching and control system is described that provides compatibility with conventional analog cameras while also accepting network IP type cameras. The system offers reduced control latency, improved recording efficiency, and more flexible display features with greatly improved performance and update rates. The system offers greatly reduced wiring and installation complexity thus improving reliability. The architecture is scalable and expandable in either the analog camera count or the IP camera count. The system integrates these two camera technologies so that the camera source or recorder is transparent to the user. Each user can control all video sources, analog, IP, or recorded, from one keyboard and one or more monitors at each work station. The unique all digital solution provides digital reliability and broadcast quality performance.

Abstract: An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.

Abstract: In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

Abstract: In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

Abstract: Foamed two-part hard surface treatment composition which is formed by the admixture of two aqueous compositions, particularly (a) an aqueous alkaline composition comprising a bleach constituent, with (b) an aqueous acidic composition comprising a peroxide constituent, which compositions are kept separate, but which are admixed immediately prior to use or upon use to form a foamed hard surface treatment composition. The foamed two-part hard surface treatment composition are particularly useful in the cleaning of hard surfaces. Preferred foamed two-part hard surface treatment composition provide both a cleaning and sanitizing or disinfecting benefit to hard surfaces, while releasing little or no free chlorine gas to the ambient air.

Abstract: In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

Abstract: A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

Abstract: A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

Abstract: A two-dimensional (2D) chemical shift correlated MR spectroscopic (COSY) sequence integrated into a new volume localization technique (90°-180°-90°) for whole body MR Spectroscopy. Using the product operator formalism, a theoretical calculation of the volume localization as well as the coherence transfer efficiencies in 2D MRS is presented. A combination of different MRI transmit/receive rf coils is used. The cross peak intensities excited by the proposed 2D sequence are asymmetric with respect to the diagonal peaks. Localized COSY spectra of cerebral frontal and occipital gray/white matter regions in fifteen healthy controls are presented.

Abstract: The inventor has designed a rotating brush, and slip ring system allowing a continuous electrical connection between a rotating wheel and stationary chassis. Used with an on dash instrument, an on tire rim pressure sensor, and wiring harness, will allow a driver to monitor the tire pressure in any of the tires whether at rest or at any speed. The on rim air pressure sensor would be mounted so as the diaphragm would be in contact with the air pressure in a tire. The slip rings are to be composed of a highly conductive material so that the electrical signal would be passed on through the harness to the electrical instrument on the dash. This system is limitless and could be used on any type machine that incorporates rotating pneumatic tires.

Abstract: Alkaline cleaning and sanitizing compositions which are essentially free of chelating agents based on organic acid compounds, especially nitrogen containing chelating agents are provided, which compositions are particularly directed for the removal of soap scum stains on hard surfaces.

Abstract: A method is disclosed for processing a silicon workpiece including a hybrid thermometer system for measuring and controlling the processing temperature where fabrication materials have been or are being applied to the workpiece. The hybrid thermometer system uses optical reflectance and another thermometer technique, such as a thermocouple and/or a pyrometer. Real-time spectral data are compared to values in a spectrum library to determine the “surface conditions”. A decision is then made based on the surface conditions as to how the temperature is measured, e.g., with optical reflectance, a pyrometer, or a thermocouple, and the temperature is measured using the appropriately selected technique. Utilizing the hybrid thermometer system, the temperature of a silicon workpiece may be accurately measured at low temperatures while accounting for the presence of fabrication materials.

Abstract: Alkaline cleaning and sanitizing compositions which are essentially free of chelating agents based on organic acid compounds, especially nitrogen containing chelating agents are provided, which compositions are particularly directed for the removal of soap scum stains on hard surfaces.

Abstract: A method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor provides a mechanism for redistributing rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper.