Patents by Inventor Albert Wan

Albert Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128635
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: December 24, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 11855333
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20230307391
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Application
    Filed: May 29, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Patent number: 11705409
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Publication number: 20230203233
    Abstract: An aqueous polyurethane dispersion and a textile are provided. The aqueous polyurethane dispersion includes water and a bio-based polyurethane. The bio-based polyurethane includes bio-based polyester polyol, hydrophilic polyol, isocyanate, and hydrophilic compound. A weight ratio of the bio-based polyester polyol to the hydrophilic polyol is 2.7:1 to 5.3:1.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Albert Wan, Yu-Ting Chen, Min-Yan Dong, Jing-Wen Tang
  • Patent number: 11515618
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20220368005
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20220204720
    Abstract: A method for decolorization of polyester fabrics is provided. The method for decolorization of polyester fabrics includes putting polyester fabrics into an extraction cell. The method for decolorization of polyester fabrics also includes making a supercritical fluid and a co-solvent flow into the extraction cell. The method for decolorization of polyester fabrics further includes adjusting the temperature in the extraction cell to be greater than or equal to the glass transition temperature of the polyester fabrics, so that the supercritical fluid and the co-solvent perform a decolorization reaction on the polyester fabrics. Moreover, the method for decolorization of polyester fabrics includes making the supercritical fluid and the co-solvent flow out of the extraction cell. The method for decolorization of polyester fabrics also includes taking the polyester fabrics out of the extraction cell.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Jung CHANG, Albert WAN, Min-Yan DONG, Jing-Wen TANG
  • Patent number: 11335655
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Patent number: 11282810
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Publication number: 20210257717
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 19, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 10978782
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20210098396
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Patent number: 10879197
    Abstract: A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang
  • Patent number: 10872842
    Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
  • Patent number: 10867882
    Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
  • Patent number: 10867940
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Publication number: 20200335477
    Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
  • Publication number: 20200335459
    Abstract: A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Ching-Hua Hsieh, Chao-Wen Shih, Han-Ping Pu, Meng-Tse Chen, Sheng-Hsiang Chiu
  • Publication number: 20200273773
    Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu