Abstract: In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip.

Abstract: The semiconductor apparatus according to the present invention includes: a second-conductivity-type first diffusion region formed on the semiconductor layer; a first-conductivity-type second diffusion region formed in the first diffusion region; a second-conductivity-type first high concentration diffusion region and a first-conductivity-type second high concentration diffusion region formed in the second diffusion region; a second-conductivity-type third high concentration diffusion region, separated by a given distance from the second diffusion region, in the first diffusion region; and a gate electrode formed above and between the first high concentration diffusion region and third high concentration diffusion region, with a gate insulation film interposed therebetween, where the gate electrode is formed overlapping the first high concentration diffusion region, and the gate electrode is electrically connected with the first high concentration diffusion region and second high concentration diffusion region

Abstract: In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than ?8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than ?8° and not more than +8° off the silicon crystal direction.

Abstract: In an embodiment of the present invention, a Trench MOSFET includes a trench region provided on a semiconductor substrate. The semiconductor substrate includes a P-type semiconductor substrate, a P-type semiconductor epitaxial layer, an N-type semiconductor body region, and a P-type semiconductor source diffusion. The substrate, the epitaxial layer, the body region, and the source diffusion are adjacently formed in this order. A P-type semiconductor channel region formed of a SiGe layer is provided on a bottom surface and a side wall of the trench region. This facilitates carrier movement in the channel region, reducing ON resistance of the Trench MOSFET. Thus, a Trench MOSFET allowing reduction in the ON resistance without reducing a breakdown voltage is realized.

Abstract: In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than ?8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than ?8° and not more than +8° off the silicon crystal direction.

Abstract: In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip.

Abstract: A frequency conversion circuit of the present invention includes: (i) a first mixer for mixing the radio frequency signal having a frequency fRF with a first oscillation signal having a frequency fLO1 so that the radio frequency signal is downconverted into an intermediate frequency signal; and (ii) a second mixer for mixing the intermediate frequency signal sent from the first mixer with two local oscillation signals so that the intermediate frequency signal is downconverted into two base-band signals having different phases. The second local oscillation signals have phases of 0° and 270°, respectively. These frequencies satisfies: fLO1=k×fRF(k>1) fLO2=fLO1/m, (m>1) k=m/(m?1). This arrangement ensures (i) a small frequency conversion circuit that can be mounted on an integrated circuit, (ii) a radio frequency receiver including the frequency conversion circuit, and (iii) a radio frequency transceiver including the radio frequency receiver.

Abstract: In one embodiment of the present invention, trench sections cause regions where source diffusion sections and body diffusion sections are formed to be partitioned into line regions. The trench sections are formed not in a straight line shape but in a zigzag shape. Two adjacent trench sections are provided to be axisymmetric, having an axis of symmetry in a longitudinal direction of the trench sections. A wide region and a narrow region are alternately formed in each of the regions, partitioned by the trench sections, in which regions the source diffusion sections and the body diffusion sections are formed. Each of the body diffusion sections is formed in the wide region. This makes it possible to realize an improved power MOSFET that achieves a reduction in an ON resistance per unit cell and an increase in a layout effect.

Abstract: A field effect transistor of the present invention includes, on a semiconductor substrate, (i) a fin section formed in a fin shape protruding from the substrate, (ii) a gate dielectric for covering a channel region section of the fin section, (iii) a gate electrode that is insulated from the channel region section by the gate dielectric and is formed on the channel region section and (iv) an insulating layer for covering a surface of the semiconductor substrate. The fin section is formed so as to extend from the semiconductor substrate through the insulating layer and protrudes outward from a surface of the insulating layer. In this way, the channel region of the fin section is physically in contact with the substrate.

Abstract: A Trench MOSFET includes a trench region (16) provided on a semiconductor substrate. The semiconductor substrate includes a P-type semiconductor substrate (1), a P-type semiconductor epitaxial layer (2), an N-type semiconductor body region (3), and a P-type semiconductor source diffusion (7). The substrate (1), the epitaxial layer (2), the body region (3), and the source diffusion (7) are adjacently formed in this order. A P-type semiconductor channel region (4) formed of a SiGe layer is provided on a bottom surface and a side wall of the trench region (16). This facilitates carrier movement in the channel region 4, reducing ON resistance of the Trench MOSFET. Thus, a Trench MOSFET allowing reduction in the ON resistance without reducing a breakdown voltage is realized.

Abstract: The oscillator includes: a first oscillator circuit in which first and second transistors cross-connected to each other are connected to a resonant circuit; and a second oscillator circuit in which third and fourth transistors cross-connected to each other are connected to a resonant circuit, wherein a coupling capacitor and coupling resistor are serially provided between a collector terminal of the first transistor and a base terminal of the fourth transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the second transistor and a base terminal of the third transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the third transistor and a base terminal of the first transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the fourth transistor and a base terminal of the second transistor.

Abstract: A variable gain amplifier circuit 1 includes an amplifier A1, an amplifier A2, an inductor L1, and an inductor L2. The amplifier A1 has a predetermined gain and is connected at a terminal to a circuit output section. The amplifier A2 has a different gain from the amplifier A1 and is connected at a terminal to the circuit output section. The inductor L1 is connected at an end to a circuit input section and at the other end to the input terminal of the amplifier A1. The inductor L2 is connected at an end to ground and at the other end to the input terminal of the amplifier A2. The inductors L1 and L2 form a transformer T. The configuration restricts input impedance variations which are dependent on the signal path taken by an input signal Vin. The input impedance and the signal source impedance remain matched. Impedance matching is preformed with the signal source with variable gain.

Abstract: A phase locked loop circuit includes a phase comparator and a charge-pump circuit. The phase comparator and the charge-pump circuit are configured to satisfy the relationship of Kp2>Kp1 in an Io??? characteristic, where Kp1 indicates a slope Kp in the case where |??|>??o, Kp2 indicates a slope Kp in the case where |??|???o, Kp being defined by Kp=dIo/d??, and ??o being a constant indicating a predetermined phase error.

Abstract: A lamination of metal wire layers forms an electromagnetic isolation structure. The metal wire layers are connected with each other by vias, so that a metal fence having a laminated structure is formed. The metal fence is provided so as to surround an element (e.g. a spiral inductor) that generates an electromagnetic field in an integrated circuit. The metal wire satisfies d??/8, WF?5?, and L??/20, where ? is a skin depth of an electromagnetic wave, c is a velocity of light, f is an operating frequency of the integrated circuit, d is a lateral-direction size of a metal-fence region, WF is a surrounding-line width of the metal fence, L is an interval between the vias, and ?=c/f is a wavelength of a signal. With this arrangement, it is possible to decrease electromagnetic coupling noises and coupling noises caused via the substrate.

Abstract: A the present invention provides an electrostatic discharge protection element to be used in a semiconductor integrated circuit providing MOSFET, comprising a thyristor and a trigger diode for triggering the thyristor into an ON-state, wherein the trigger diode provides an n-type cathode high concentration impurity region, a p-type anode high concentration impurity region and a gate formed between the two high concentration impurity regions, the gate being composed of the same material as that of a gate of MOSFET forming the semiconductor integrated circuit, and the thyristor provided with a p-type high concentration impurity region that forms a cathode and an n-type high concentration impurity region that forms an anode, and the p-type high concentration impurity region provides in a p well and connected to a resistor and/or the n-type high concentration impurity region provided in an n well and connected to a resistor.

Abstract: A lamination of metal wire layers forms an electromagnetic isolation structure. The metal wire layers are connected with each other by vias, so that a metal fence having a laminated structure is formed. The metal fence is provided so as to surround an element (e.g. a spiral inductor) that generates an electromagnetic field in an integrated circuit. The metal wire satisfies d≦&lgr;/8, WF≧5&dgr;, and L≦&lgr;/20, where &dgr; is a skin depth of an electromagnetic wave, c is a velocity of light, f is an operating frequency of the integrated circuit, d is a lateral-direction size of a metal-fence region, WF is a surrounding-line width of the metal fence, L is an interval between the vias, and &lgr;=c/f is a wavelength of a signal. With this arrangement, it is possible to decrease electromagnetic coupling noises and coupling noises caused via the substrate.

Abstract: A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.

Abstract: A the present invention provides an electrostatic discharge protection element to be used in a semiconductor integrated circuit providing MOSFET, comprising a thyristor and a trigger diode for triggering the thyristor into an ON-state, wherein the trigger diode provides an n-type cathode high concentration impurity region, a p-type anode high concentration impurity region and a gate formed between the two high concentration impurity regions, the gate being composed of the same material as that of a gate of MOSFET forming the semiconductor integrated circuit, and the thyristor provided with a p-type high concentration impurity region that forms a cathode and an n-type high concentration impurity region that forms an anode, and the p-type high concentration impurity region provides in a p well and connected to a resistor and/or the n-type high concentration impurity region provided in an n well and connected to a resistor.

Abstract: An active inductor includes an MOSFET having a gate, a drain serving as an output terminal and a grounded source, the MOSFET having a transconductance gm1, and a capacitor having opposite ends, one of which is grounded and the other of which is connected to the gate of the MOSFET and to a voltage-controlled constant current source having a transconductance gm, the capacitor having a capacitance C, the active inductor being operative with a small-signal output impedance Zo between the output terminal and the ground expressed as Zo=j&ohgr;{C/(gm1·gm)} (wherein &ohgr; is an angular frequency) and with an inductance Leq expressed as Leq={C/(gm1·gm)}.

Abstract: A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.