Abstract: A semiconductor device comprises: gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.

Abstract: A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.

Abstract: A SOI.MOSFET includes: a substrate; a buried oxide film formed on the substrate; a top semiconductor layer formed on the buried oxide film; a gate electrode formed on the top semiconductor layer with a gate oxide film interposed therebetween; source/drain regions of a second conductivity type formed in the top semiconductor layer and on both sides of the gate electrode; and an embedded region of the second conductivity type which is disposed in the top semiconductor layer and between the source/drain regions and is separated from the source/drain regions and from a top semiconductor/gate oxide interface.

Abstract: A FEC-DRAM of 3 elements/2 bits type having a stack capacitor of increased capacitance to ensure integration with an increased density. The stack capacitor is formed as embedded in a trench, and local wiring is provided to form an electric contact on an element isolation region. When required, the stack capacitor is made to extend onto a word line region. The stack capacitor is given an increased surface area and a greater capacitance, consequently reducing the area occupied and making it possible to provide DRAMs with a higher packing density.

Abstract: On a p-type semiconductor substrate (well region) there are arranged apart from each other an n-type source region and an n-type drain region, a channel region therebetween, and a gate electrode. A pair of p-type channel diffusion regions doped more heavily than the substrate are formed along the channel boundary between the source region and the drain region and the substrate. The channel diffusion region below the drain region is doped with an n-type impurity to achieve a lower active impurity concentration relative to that in the channel diffusion region below the gate electrode.

Abstract: A semiconductor device with a non-uniformly and lightly doped channel comprises a gate electrode formed on a silicon substrate of first conductivity through the intermediary of a gate oxide dielectric film, and an extension of each side walls of the gate electrode composed of a thin polysilicon layer which is substantially thinner than the gate electrode, the silicon substrate having a channel region in which its central part is doped with ions of first conductivity at a concentration higher than in the silicon substrate and its part below the thin polysilicon layer is doped with ions of first conductivity at a concentration higher than in the central part, and having at an outer region of the channel region a source-drain region doped with ions of second conductivity.

Abstract: A process for fabricating a semiconductor device having a non-uniformly and lightly doped channel comprising the steps of forming on a Si substrate an isolation region of a field oxide and an active region of a thin SiO.sub.2 layer; performing first channel doping by implanting first conductivity type ions; after removing said thin SiO.sub.2 layer, forming a gate oxide dielectric and a gate electrode thereon; performing a second channel doping by implanting said type ions; depositing a thin polysilicon layer; depositing a SiO.sub.2 layer on said thin polysilicon layer; etching to remove a portion of said SiO.sub.2 layer and thin polysilicon layer to form a side wall; and implanting second conductivity type ions followed by heat treatment to provide source and drain regions.

Abstract: A method for forming a contact portion which comprises holing a contact hole in a dielectric layer formed on a silicon substrate, protecting at least exposed portion of the silicon substrate at the bottom of the contact hole with TiW film and then depositing tungsten in the contact hole by CVD method.

Abstract: A static RAM cell including first and second bulk transistors having gate electrodes extended over an element isolation region and forming a flip-flop, third and fourth bulk transistors having source and drain regions and formed adjacently to the element isolation region, a first conductive strap layer for self-aligning the gate electrode of the first bulk transistor with the source or drain region of the third bulk transistor, and a second conductive strap layer for self-aligning the gate electrode of the second bulk transistor with the source or drain region of the fourth bulk transistor.

Abstract: A semiconductor thin film formed over a substrate and having drain and source regions each being of a conductivity type and a channel region of another conductivity type defined between the drain and source regions, a gate electrode(s) formed over and/or below the channel region of the semiconductor thin film through an insulating layer(s), a pair of electrodes being connected to the drain and source regions of the semiconductor thin film, in which said source region is placed in a self-aligned manner and adjoined to said channel region, while a drain-offset region is defined between said channel region and said drain region in a self-aligned manner.

Abstract: A method for manufacturing a semiconductor device by (i) depositing a first insulating layer over a semiconductor substrate having a polysilicon gate, and then opening a first contact hole so as to form a first insulating film, (ii) depositing a second polysilicon layer over the semiconductor substrate including the first contact hole, and then patterning the same so as to form a second polysilicon film, (iii) depositing a second insulating film over the semiconductor substrate including the second polysilicon film, and then opening a second contact hole so as to form a second insulating film, (iv) depositing a third polysilicon layer over the semiconductor substrate including the second contact hole, and then patterning the same as to form a third polysilicon film as a capacitor bottom electrode, (v) implanting ions in the second polysilicon film in a region other than a capacitor formation region so as to form a source/drain region, (vi) depositing a third insulating layer over the whole surface, and then o

Abstract: A double-gated MOS type semiconductor memory device having a pair of inverters each of which comprises a bulk MOS transistor formed in a semiconductor substrate and having a first gate electrode on the substrate, and a complementary type MOS transistor stacked over and connected with the bulk MOS transistor, the complementary tyupe MOS transistor being composed of a first insulating film, a semiconductor active layer, a second insulating film and a second gate electrode, laminated upwardly in this order on the first gate electrode, and a process for preparing the double-gated MOS type semiconductor memory device.